Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
106
capability of the requesting agent. For the Pentium
Pro processor, DSZ#= 00, always.
A.26 EXF[4:0]# (I/O)
The EXF[4:0]# signals are the Extended Function
signals and are transferred on the Ab[7:3]# signals
by the request initiator during the second clock of the
Request Phase. The signals specify any special
functional requirement associated with the
transaction based on the requester mode or
capability. The signals are defined in Table 51.
Table 51. EXF[4:0]# Signal Definitions
EXF NAME External Functionality When Activated
EXF4# SMMEM# SMM Mode After entering SMM mode
EXF3# SPLCK# Split Lock The first transaction of a split bus lock
operation
EXF2# Reserved Reserved
EXF1# DEN# Defer Enable The transactions for which Defer or Retry
Response is acceptable.
EXF0# Reserved Reserved
A.27 FERR# (O)
The FERR# signal is the PC Compatibility group
Floating-point Error signal. The Pentium Pro
processor asserts FERR# when it detects an
unmasked floating-point error. FERR# is similar to
the ERROR# signal on the Intel387™ coprocessor.
FERR# is included for compatibility with systems
using DOS-type floating-point error reporting.
A.28 FLUSH# (I)
When the FLUSH# input signal is asserted, the
Pentium Pro processor bus agent writes back all
internal cache lines in the Modified state and
invalidates all internal cache lines. At the completion
of a flush operation, the Pentium Pro processor
issues a Flush Acknowledge transaction to indicate
that the cache flush operation is complete. The
Pentium Pro processor stops caching any new data
while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous input. However, to
guarantee recognition of this signal following an I/O
write instruction, FLUSH# must be valid along with
RS[2:0]# in the Response Phase of the
corresponding I/O Write bus transaction. In FRC
mode, FLUSH# must be synchronous to BCLK.
On the active-to-inactive transition of RESET#, each
Pentium Pro processor bus agent samples FLUSH#
to determine its power-on configuration. See
Table 44.
A.29 FRCERR (I/O)
The FRCERR signal is the Error group Functional-
redundancy-check Error signal. If two Pentium Pro
processors are configured in an FRC pair, as a
single “logical” processor, then the checker
processor asserts FRCERR if it detects a mismatch
between its internally sampled outputs and the
master processor’s outputs. The checker’s FRCERR
output pin is connected to the master’s FRCERR
input pin.
For point-to-point connections, the checker always
compares against the master’s outputs. For bussed
single-driver signals, the checker compares against
the signal when the master is the only allowed driver.
For bussed multiple-driver Wire-OR signals, the
checker compares against the signal only if the
master is expected to drive the signal low.
FRCERR is also toggled during the Pentium Pro
processor’s reset action. A Pentium Pro processor
asserts FRCERR for approximately 1 second after
RESET’s active-to-inactive transition if it executes its
built-in self-test (BIST). When BIST execution