Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
105
A.21 DEN# (I/0)
The DEN# signal is the defer-enable signal. It is
driven to the bus on the second clock of the Request
Phase on the EXF1#/Ab4# pin. DEN# is asserted to
indicate that the transaction can be deferred by the
responding agent.
A.22 DEP[7:0]# (I/O)
The DEP[7:0]# signals are the data bus ECC
protection signals. They are driven during the Data
Phase by the agent responsible for driving D[63:0]#.
The DEP[7:0]# signals provide optional ECC
protection for the data bus. During power-on
configuration, DEP[7:0]# signals can be enabled for
either ECC checking or no checking.
The ECC error correcting code can detect and
correct single-bit errors and detect double-bit or
nibble errors. The
Pentium® Pro Processor
Developer’s Manual, Volume 1: Specifications
(Order
Number 242690) provides more information about
ECC.
DEP[7:0]# provide valid ECC for the entire data bus
on each data clock, regardless of which bytes are
valid. If checking is enabled, receiving agents check
the ECC signals for all 64 data signals.
A.23 DID[7:0]# (I/O)
The DID[7:0]# signals are Deferred Identifier signals.
They are transferred using A[23:16]# signals by the
request initiator. They are transferred on Ab[23:16]#
during the second clock of the Request Phase on all
transactions, but only defined for deferrable
transactions (DEN# asserted). DID[7:0]# is also
transferred on Aa[23:16]# during the first clock of the
Request Phase for Deferred Reply transactions.
The deferred identifier defines the token supplied by
the request initiator. DID[7:4]# carry the request
initiators’ agent identifier and DID[3:0]# carry a
transaction identifier associated with the request.
This configuration limits the bus specification to 16
bus masters with each one of the bus masters
capable of making up to sixteen requests.
Every deferrable transaction issued on the Pentium
Pro processor bus which has not been guaranteed
completion (has not successfully passed its Snoop
Result Phase) will have a unique Deferred ID. This
includes all outstanding transactions which have not
had their snoop result reported, or have had their
snoop results deferred. After a deferrable transaction
passes its Snoop Result Phase without DEFER#
asserted, its Deferred ID may be reused. Similarly,
the deferred ID of a transaction which was deferred
may be reused after the completion of the snoop
window of the deferred reply.
DID[7]# indicates the agent type. Symmetric agents
use 0. Priority agents use 1. DID[6:4]# indicates the
agent ID. Symmetric agents use their arbitration ID.
The Pentium Pro processor has four symmetric
agents, so does not assert DID[6]#. DID[3:0]#
indicates the transaction ID for an agent. The
transaction ID must be unique for all transactions
issued by an agent which have not reported their
snoop results.
Table 50. DID[7:0]# Encoding
DID[7] DID[6:4] DID[3:0]
Agent Type Agent ID Transaction ID
The Deferred Reply agent transmits the DID[7:0]#
(Ab[23:16]#) signals received during the original
transaction on the Aa[23:16]# signals during the
Deferred Reply transaction. This process enables the
original request initiator to make an identifier match
and wake up the original request waiting for
completion.
A.24 DRDY# (I/O)
The DRDY# signal is the Data Phase data-ready
signal. The data driver asserts DRDY# on each data
transfer, indicating valid data on the data bus. In a
multi-cycle data transfer, DRDY# can be deasserted
to insert idle clocks in the Data Phase. During a line
transfer, DRDY# is active for four clocks. During a
partial 1-to-8 byte transfer, DRDY# is active for one
clock. If a data transfer is exactly one clock, then the
entire Data Phase may consist of only one clock
active DRDY# and inactive DBSY#. If DBSY# is
asserted for a 1-to-8 byte transfer, then the data bus
is not released until one clock after DBSY# is
deasserted.
A.25 DSZ[1:0]# (I/O)
The DSZ[1:0]# signals are the data-size signals.
They are transferred on REQb[4:3]# signals in the
second clock of Request Phase by the requesting
agent. The DSZ[1:0]# signals define the data transfer