Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
104
require four data transfer clocks with valid data on all
eight bytes. Partial transfers require one data transfer
clock with valid data on the byte(s) indicated by
active byte enables BE[7:0]#. Data signals not valid
for a particular transfer must still have correct ECC (if
data bus ECC is selected). If BE0# is asserted,
D[7:0]# transfers the least significant byte. If BE7# is
asserted, D[63:56]# transfers the most significant
byte.
The data driver asserts DRDY# to indicate a valid
data transfer. If the Data Phase involves more than
one clock the data driver also asserts DBSY# at the
beginning of the Data Phase and de-asserts DBSY#
no earlier than on the same clock that it performs the
last data transfer.
A.19 DBSY# (I/O)
The DBSY# signal is the Data-bus Busy signal. It
indicates that the data bus is busy. It is asserted by
the agent responsible for driving the data during the
Data Phase, provided the Data Phase involves more
than one clock. DBSY# is asserted at the beginning
of the Data Phase and may be deasserted on or after
the clock on which the last data is driven. The data
bus is released one clock after DBSY# is
deasserted.
When normal read data is being returned, the Data
Phase begins with the Response Phase. Thus the
agent returning read data can assert DBSY# when
the transaction reaches the top of the In-order Queue
and it is ready to return response on RS[2:0]#
signals. In response to a write request, the agent
driving the write data must drive DBSY# active after
the write transaction reaches the top of the In-order
Queue and it sees active TRDY# with inactive
DBSY# indicating that the target is ready to receive
data. For an implicit writeback response, the snoop
agent must assert DBSY# active after the target
memory agent of the implicit writeback asserts
TRDY#. Implicit writeback TRDY# assertion begins
after the transaction reaches the top of the In-order
Queue, and TRDY# de-assertion associated with the
write portion of the transaction, if any is completed. In
this case, the memory agent guarantees assertion of
implicit writeback response in the same clock in
which the snooping agent asserts DBSY#.
A.20 DEFER# (I)
The DEFER# signal is the defer signal. It is asserted
by an agent during the Snoop Phase to indicate that
the transaction cannot be guaranteed in-order
completion. Assertion of DEFER# is normally the
responsibility of the addressed memory agent or I/O
agent. For systems that involve resources on a
system bus other than the Pentium Pro processor
bus, a bridge agent can accept the DEFER#
assertion responsibility on behalf of the addressed
agent.
When HITM# and DEFER# are both active during the
Snoop Phase, HITM# is given priority and the
transaction must be completed with implicit writeback
response. If HITM# is inactive, and DEFER# active,
the agent asserting DEFER# must complete the
transaction with a Deferred or Retry response.
If DEFER# is inactive, or HITM# is active, then the
transaction is committed for in-order completion and
snoop ownership is transferred normally between the
requesting agent, the snooping agents, and the
response agent.
If DEFER# is active with HITM# inactive, the
transaction commitment is deferred. If the defer
agent completes the transaction with a retry
response, the requesting agent must retry the
transaction. If the defer agent returns a deferred
response, the requesting agent must freeze snoop
state transitions associated with the deferred
transaction and issues of new order-dependent
transactions until the corresponding deferred reply
transaction. In the meantime, the ownership of the
deferred address is transferred to the defer agent
and it must guarantee management of conflicting
transactions issued to the same address.
If DEFER# is active in response to a newly issued
bus-lock transaction, the entire bus-locked operation
is re-initiated regardless of HITM#. This feature is
useful for a bridge agent in response to a split bus-
locked operation. It is recommended that the bridge
agent extend the Snoop Phase of the first transaction
in a split locked operation until it can either guarantee
ownership of all system resources to enable
successful completion of the split sequence or assert
DEFER# followed by a Retry Response to abort the
split sequence.