Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
102
mechanism enables independent control on every
new request generation.
If BNR# is deasserted on two consecutive sampling
points, new requests can be freely generated on the
bus. After receiving a new transaction, a bus agent
can require an address stall due to an anticipated
transaction-queue overflow condition. In response,
the bus agent can assert BNR#, three clocks from
active ADS# assertion and create a bus stall. Once a
bus stall is created, the bus remains stalled until
BNR# is sampled asserted on subsequent sampling
points.
A.13 BP[3:2]# (I/O)
The BP[3:2]# signals are the System Support group
Breakpoint signals. They are outputs from the
Pentium Pro processor that indicate the status of
breakpoints.
A.14 BPM[1:0]# (I/O)
The BPM[1:0]# signals are more System Support
group breakpoint and performance monitor signals.
They are outputs from the Pentium Pro processor
that indicate the status of breakpoints and
programmable counters used for monitoring Pentium
Pro processor performance.
A.15 BPRI# (I)
The BPRI# signal is the Priority-agent Bus Request
signal. The priority agent arbitrates for the bus by
asserting BPRI#. The priority agent is always be the
next bus owner. Observing BPRI# active causes the
current symmetric owner to stop issuing new
requests, unless such requests are part of an
ongoing locked operation.
If LOCK# is sampled inactive two clocks from BPRI#
driven asserted, the priority agent can issue a new
request within four clocks of asserting BPRI#. The
priority agent can further reduce its arbitration latency
to two clocks if it samples active ADS# and inactive
LOCK# on the clock in which BPRI# was driven
active and to three clocks if it samples active ADS#
and inactive LOCK# on the clock in which BPRI#
was sampled active. If LOCK# is sampled active, the
priority agent must wait for LOCK# deasserted and
gains bus ownership in two clocks after LOCK# is
sampled deasserted. The priority agent can keep
BPRI# asserted until all of its requests are completed
and can release the bus by de-asserting BPRI# as
early as the same clock edge on which it issues the
last request.
On observation of active AERR#, RESET#, or
BINIT#, BPRI# must be deasserted in the next clock.
BPRI# can be reasserted in the clock after sampling
the RESET# active-to-inactive transition or three
clocks after sampling BINIT# active and RESET#
inactive. On AERR# assertion, if the priority agent is
in the middle of a bus-locked operation, BPRI# must
be re-asserted after two clocks, otherwise BPRI#
must stay inactive for at least 4 clocks.
After the RESET# inactive transition, Pentium Pro
processor bus agents begin BPRI# and BNR#
sampling on BNR# sample points. When both BNR#
and BPRI# are observed inactive on a BNR#
sampling point, the APIC units in Pentium Pro
processors on a common APIC bus are
synchronized.
A.16 BR0#(I/O), BR[3:1]# (I)
The BR[3:0]# pins are the physical bus request pins
that drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating
manner to individual processor pins. Table 48 gives
the rotating interconnect between the processor and
bus signals.