Specifications

E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz
101
A.10 BERR# (I/O)
The BERR# signal is the Error group Bus Error
signal. It is asserted to indicate an unrecoverable
error without a bus protocol violation.
The BERR# protocol is as follows: If an agent
detects an unrecoverable error for which BERR# is a
valid error response and BERR# is sampled inactive,
it asserts BERR# for three clocks. An agent can
assert BERR# only after observing that the signal is
inactive. An agent asserting BERR# must deassert
the signal in two clocks if it observes that another
agent began asserting BERR# in the previous clock.
BERR# assertion conditions are defined by the
system configuration. Configuration options enable
the BERR# driver as follows:
• Enabled or disabled
• Asserted optionally for internal errors along with
IERR#
• Optionally asserted by the request initiator of a
bus transaction after it observes an error
• Asserted by any bus agent when it observes an
error in a bus transaction
BERR# sampling conditions are also defined by the
system configuration. Configuration options enable
the BERR# receiver to be enabled or disabled. When
the bus agent samples an active BERR# signal and if
MCE is enabled, the Pentium Pro processor enters
the Machine Check Handler. If MCE is disabled,
typically the central agent forwards BERR# as an
NMI to one of the processors. The Pentium Pro
processor does not support BERR# sampling
(always disabled).
A.11 BINIT# (I/O)
The BINIT# signal is the bus initialization signal. If the
BINIT# driver is enabled during the power on
configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future information.
The BINIT# protocol is as follows: If an agent detects
an error for which BINIT# is a valid error response,
and BINIT# is sampled inactive, it asserts BINIT# for
three clocks. An agent can assert BINIT# only after
observing that the signal is inactive. An agent
asserting BINIT# must deassert the signal in two
clocks if it observes that another agent began
asserting BINIT# in the previous clock.
If BINIT# observation is enabled during power-on
configuration, and BINIT# is sampled asserted, all
bus state machines are reset. All agents reset their
rotating ID for bus arbitration to the state after reset,
and internal count information is lost. The L1 and L2
caches are not affected.
If BINIT# observation is disabled during power-on
configuration, BINIT# is ignored by all bus agents
except a central agent that must handle the error in a
manner appropriate to the system architecture.
A.12 BNR# (I/O)
The BNR# signal is the Block Next Request signal in
the Arbitration group. The BNR# signal is used to
assert a bus stall by any bus agent who is unable to
accept new bus transactions to avoid an internal
transaction queue overflow. During a bus stall, the
current bus owner cannot issue any new
transactions.
Since multiple agents might need to request a bus
stall at the same time, BNR# is a wire-OR signal. In
order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple
drivers, BNR# is activated on specific clock edges
and sampled on specific clock edges. A valid bus
stall involves assertion of BNR# for one clock on a
well-defined clock edge (T1), followed by de-
assertion of BNR# for one clock on the next clock
edge (T1+1). BNR# can first be sampled on the
second clock edge (T1+1) and must always be
ignored on the third clock edge (T1+2). An extension
of a bus stall requires one clock active (T1+2), one
clock inactive (T1+3) BNR# sequence with BNR#
sampling points every two clocks (T1+1, T1+3,...).
After the RESET# active-to-inactive transition, bus
agents might need to perform hardware initialization
of their bus unit logic. Bus agents intending to create
a request stall must assert BNR# in the clock after
RESET# is sampled inactive.
After BINIT# assertion, all bus agents go through a
similar hardware initialization and can create a
request stall by asserting BNR# four clocks after
BINIT# assertion is sampled.
On the first BNR# sampling clock that BNR# is
sampled inactive, the current bus owner is allowed to
issue one new request. Any bus agent can
immediately reassert BNR# (four clocks from the
previous assertion or two clocks from the previous
de-assertion) to create a new bus stall. This throttling