Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
100
when ASZ[1:0]# equals 00. All observing bus agents
that support the 64GByte (36- bit) address space
must respond to the transaction when ASZ[1:0]#
equals 00B or 01B.
A.7 ATTR[7:0]# (I/O)
The ATTR[7:0]# signals are the attribute signals.
They are driven by the request initiator during the
second Request Phase clock on the Ab[31:24]# pins.
The ATTR[7:0]# signals are valid for all transactions.
The ATTR[7:3]# are reserved and undefined. The
ATTR[2:0]# are driven based on the Memory Range
Register attributes and the Page Table attributes.
Table 47. defines ATTR[3:0]# signals.
A.8 BCLK (I)
The BCLK (clock) signal is the Execution Control
group input signal. It determines the bus frequency.
All agents drive their outputs and latch their inputs on
the BCLK rising edge.
The BCLK signal indirectly determines the Pentium
Pro processor’s internal clock frequency. Each
Pentium Pro processor derives its internal clock from
BCLK by multiplying the BCLK frequency by a ratio
as defined and allowed by the power-on
configuration. See Table 42.
All external timing parameters are specified with
respect to the BCLK signal.
A.9 BE[7:0]# (I/O)
The BE[7:0]# signals are the byte-enable signals.
They are driven by the request initiator during the
second Request Phase clock on the Ab[15:8]# pins.
These signals carry various information depending
on the REQ[4:0]# value.
For memory or I/O transactions (REQa[4:0]# =
{10000B, 10001B, XX01XB, XX10XB, XX11XB}) the
byte-enable signals indicate that valid data is
requested or being transferred on the corresponding
byte on the 64 bit data bus. BE0# indicates D[7:0]# is
valid, BE1# indicates D[15:8]# is valid,..., BE7#
indicates D[63:56]# is valid.
For Special transactions ((REQa[4:0]# = 01000B)
and (REQb[1:0]# = 01B)), the BE[7:0]# signals carry
special cycle encodings as defined in Table 46. All
other encodings are reserved.
Table 46. Special Transaction Encoding on
BE[7:0]#
BE[7:0]# Special Cycle
0000 0000 Reserved
0000 0001 Shutdown
0000 0010 Flush
0000 0011 Halt
0000 0100 Sync
0000 0101 Flush Acknowledge
00000 0110 Stop Clock Acknowledge
00000 0111 SMI Acknowledge
Other Reserved
For Deferred Reply, Interrupt Acknowledge, and
Branch Trace Message transactions, the BE[7:0]#
signals are undefined.
Table 47. ATTR[7:0]# Field Descriptions
ATTR[7:3]# ATTR[2]# ATTR[1:0]#
XXXXX X 11 10
01
00
Reserved Potentially
Speculatable
Write-Back Write-Protect
Write-Through
UnCacheable