Specifications

PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E
10
RS - Reservation Station
MIU - Memory Interface Unit
RRF - Retirement Register File
R
S
MIU
RRF
From To
Instruction Pool
To/from DCache
Figure 5. Inside the Retire Unit
MOB - Memory Order Buffer
AGU - Address Generation Unit
ROB - ReOrder Buffer
Mem
I/F
MOB
DCache
From
AGU
To/from
Instruction
Pool (ROB)
Sys Mem
L2 Cache
Figure 6. Inside the Bus Interface Unit
There are two types of memory access: loads and
stores. Loads only need to specify the memory
address to be accessed, the width of the data being
retrieved, and the destination register. Loads are
encoded into a single µop.
Stores need to provide a memory address, a data
width, and the data to be written. Stores therefore
require two µops, one to generate the address, and
one to generate the data. These µops must later re-
combine for the store to complete.
Stores are never performed speculatively since there
is no transparent way to undo them. Stores are also
never reordered among themselves. A store is
dispatched only when both the address and the data
are available and there are no older stores awaiting
dispatch.
A study of the importance of memory access
reordering concluded:
• Stores must be constrained from passing other
stores, for only a small impact on performance.