Specifications

ManualsBrandsAMD ManualsComputer equipment-K6-2/450 - MHz Processor

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Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer products may have minor

variations to these specifications known as errata. Contact your local sales office or distributor to obtain the latest specifications before

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Available at 150 MHz, 166 MHz,

180 MHz and 200MHz core speeds

Binary compatible with applications

running on previous members of the

Intel microprocessor family

Optimized for 32-bit applications

running on advanced 32-bit operating

systems

Dynamic Execution microarchitecture

Single package includes Pentium

Pro

processor CPU, cache and system bus

interface

Scalable up to four processors and

4 GB memory

Separate dedicated external system

bus, and dedicated internal full-speed

cache bus

8 KB / 8 KB separate data and

instruction, non-blocking, level one

cache

Available with integrated 256 KB or

512 KB, non-blocking, level two cache

on package

Data integrity and reliability features

include ECC, Fault Analysis/Recovery,

and Functional Redundancy Checking

Upgradable to a Future OverDrive

processor

The Pentium

Pro processor family is Intel's next generation of performance for high-end desktops, workstations

and servers. The family consists of processors at 150 MHz and higher and is easily scalable to up to four

microprocessors in a multiprocessor system. The Pentium Pro processor delivers more performance than

previous generation processors through an innovation called Dynamic Execution. This is the next step beyond

the superscalar architecture implemented in the Pentium processor. This makes possible the advanced 3D

visualization and interactive capabilities required by today's high-end commercial and technical applications and

tomorrow's emerging applications. The Pentium Pro processor also includes advanced data integrity, reliability,

and serviceability features for mission critical applications.

The Pentium Pro processor may contain design defects or errors known as errata. Current characterized errata

are available upon request.

PENTIUM® PRO PROCESSOR AT

150 MHz, 166 MHz, 180 MHz and

200 MHz

Summary of content (114 pages)

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E n n n n n n PENTIUM® PRO PROCESSOR AT 150 MHz, 166 MHz, 180 MHz and 200 MHz n Available at 150 MHz, 166 MHz, 180 MHz and 200MHz core speeds Binary compatible with applications running on previous members of the Intel microprocessor family n Optimized for 32-bit applications running on advanced 32-bit operating systems n Dynamic Execution microarchitecture Single package includes Pentium® Pro processor CPU, cache and system bus interface Scalable up to four processors and 4 GB memory n n Separate d
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz CONTENTS PAGE E PAGE 1.0. INTRODUCTION ...............................................4 6.0. THERMAL SPECIFICATIONS ........................59 1.1. TERMINOLOGY.............................................4 6.1. Thermal Parameters.....................................60 1.2. REFERENCES...............................................4 6.2. Thermal Analysis ..........................................62 2.0. PENTIUM® PRO PROCESSOR ARCHITECTURE OVERVIEW.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz CONTENTS (Contd.) PAGE PAGE A.20 DEFER# (I) ...............................................104 A.39 PICCLK (I).................................................109 A.21 DEN# (I/0) .................................................105 A.40 PICD[1:0] (I/O) ..........................................109 A.22 DEP[7:0]# (I/O) .........................................105 A.41 PWRGOOD (I) ..........................................109 A.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 1.0. INTRODUCTION The Pentium Pro processor is the next in the Intel386™, Intel486™, and Pentium family of processors. The Pentium Pro processor implements a Dynamic Execution microarchitecture—a unique combination of multiple branch prediction, data flow analysis, and speculative execution. The Pentium Pro processor is upgradable by a future OverDrive processor and matching voltage regulator module described in Section 8.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz “execute” phases, and opens up a wide instruction window using an instruction pool. This approach allows the “execute” phase of the Pentium Pro processor to have much more visibility into the program’s instruction stream so that better scheduling may take place. It requires the instruction “fetch/decode” phase of the Pentium Pro processor to be much more intelligent in terms of predicting program flow.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Example 1. A Typical Code Fragment r1 r2 r5 r6 <= <= <= <= mem [r0] r1 + r2 r5 + r1 r6 - r3 The cache miss on instruction 1 will take many internal clocks, so the Pentium Pro processor core continues to look ahead for other instructions that could be speculatively executed, and is typically looking 20 to 30 instructions in front of the instruction pointer.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz System Bus L2 Cache Bus Interface Unit L1 ICache L1 DCache Fetch Fetch/ Decode Unit Load Dispatch /Execute Unit Store Retire Unit Instruction Pool Figure 2. The Three Core Engines Interface with Memory via Unified Caches • 2.2.1. THE FETCH/DECODE UNIT Figure 3 shows a more detailed view of the Fetch/Decode Unit. The ICache is a local instruction cache.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E From BIU ICache Next_IP BIU - Bus Interface Unit ID - Instruction Decoder BTB - Branch Target Buffer MIS - Microcode Instruction Sequencer RAT - Register Alias Table ROB - ReOrder Buffer BTB ID (x3) MIS RAT Allocate To Instruction Pool (ROB) Figure 3. Inside the Fetch/Decode Unit The ICache fetches the cache line corresponding to the index from the Next_IP, and the next line, and presents 16 aligned bytes to the decoder.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz RS Port 0 To/from Instruction Pool (ROB) FEU IEU Port 1 JEU IEU Port 2 AGU Port 3,4 AGU RS - Reservation Station EU - Execution Unit FEU - Floating Point EU IEU - Integer EU JEU - Jump EU AGU - Address Generation Unit ROB - ReOrder Buffer Load Store Figure 4. Inside the Dispatch/Execute Unit Note that the actual algorithm employed by this execution-scheduling process is vitally important to performance.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E To/from DCache R MIU S RS - Reservation Station MIU - Memory Interface Unit RRF - Retirement Register File RRF From To Instruction Pool Figure 5. Inside the Retire Unit Sys Mem L2 Cache MOB - Memory Order Buffer AGU - Address Generation Unit ROB - ReOrder Buffer MOB Mem I/F DCache From AGU To/from Instruction Pool (ROB) Figure 6. Inside the Bus Interface Unit There are two types of memory access: loads and stores.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz • Stores can be constrained from passing loads, for an inconsequential performance loss. • Constraining loads from passing other loads or stores has a significant impact on performance. The Memory Order Buffer (MOB) allows loads to pass other loads and stores by acting like a reservation station and re-order buffer. It holds suspended loads and stores and re-dispatches them when a blocking condition (dependency or resource) disappears. 2.3.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz HALT, the Pentium Pro processor will recognize all interrupts and snoops. Auto HALT power is specified assuming no snoop hits or interrupts occur. The low-power stand-by mode of Stop Grant or Auto HALT can be defined by a Low-Power Enable configuration bit to be either the lowest power achievable by the Pentium Pro processor (Stop Grant power), or a power state in which the clock distribution is left running (Idle power).
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Vss Current Vcc Current Averaged Vcc Current Load-Change Transient Switching Transient Switching Transient nS Figure 8. Transient Types Bulk capacitance with a low Effective Series Resistance (ESR) should also be placed near the Pentium Pro processor in order to handle changes in average current between the low-power and normal operating states.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 3.4.3. PHASE LOCK LOOP (PLL) DECOUPLING Isolated analog decoupling is required for the internal PLL. This should be equivalent to 0.1µF of ceramic capacitance. The capacitor should be type Y5R or better and should be across the PLL1 and PLL2 pins of the Pentium Pro processor. (“Y5R” implies ±15% tolerance over the temperature range -30°C to +85°C.) 3.5.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz BCLK RESET# CRESET# Compatibility Ratio pins# ≤ Final Ratio Final Ratio Figure 9. Timing Diagram of Clock Ratio Signals Using CRESET# (CMOS reset), the circuit in Figure 10 can be used to share the pins. The pins of the processors are bussed together to allow any one of them to be the compatibility processor. The component used as the multiplexer must not have outputs that drive higher than 3.3 V in order to meet the Pentium Pro processor’s 3.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 3.3V 1KΩ A20M# IGNNE# LINT1/NMI LINT0/INTR 3.3V Mux Set Ratio: P6 P6 ® Pentium P6 Pro Processor 1KΩ CRESET# Figure 10. Example Schematic for Clock Ratio Pin Sharing Table 1. Voltage Identification Definition 1,2 Note: In order to support different frequency multipliers to each processor, the design shown above would require four multiplexers 3.6.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Support for a wider range of VID settings will benefit the system in meeting the power requirements of future Pentium Pro processors. Note that the ‘1111’ (or all opens) ID can be used to detect the absence of a processor in a given socket as long as the power supply used does not affect these lines. In a multiprocessor system, be cautious when including empty Pentium Pro processor sockets in the scan chain.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz both processors. Also note the timing requirements for PICCLK with respect to BCLK. With FRC enabled, PICCLK must be ¼X BCLK and E synchronized with respect to BCLK. PICCLK must always lag BCLK by at least 1 ns and no more than 5 ns. Table 2.
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E 3.9. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz PWRGOOD PWRGOOD is a 3.3 V tolerant input. It is expected that this signal will be a clean indication that clocks and the system 3.3 V, 5 V and VCCP supplies are stable and within their specifications. Clean implies that the signal will remain low, (capable of sinking leakage current) without glitches, from the time that the power supplies are turned on until they come within specification.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz be connected to ground (VSS). A resistor must also be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for fully testing the processor after board assembly. For unused pins, it is suggested that ~10KΩ resistors be used for pull-ups (except for PICD[1:0] discussed above), and ~1KΩ resistors be used as pull-downs.
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E 3.13. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz DC Specifications Table 9 through Table 7 list the DC specifications associated with the Pentium Pro processor. Specifications are valid only while meeting the processor specifications for case temperature, clock frequency and input voltages. Care should be taken to read all notes associated with each parameter. See Section 3.3. for an explanation of voltage plans for Pentium Pro processors. See Section 8.4.1.1.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 5. Power Specifications 1 Symbol PMax Parameter Thermal Design Power Min ISGntP VCCP Stop Grant Current ISGntS ICCP VCCS Stop Grant Current VCCP Current ICCS ICC5 TC VCCS Current 5 V Supply Current Operating Case Temp. Max 29.2 35.0 31.7 35.0 37.9 Unit W W W W W 0.3 0.3 1.0 1.2 A A 0 0 9.9 11.2 10.1 11.2 12.4 A A A A A A 0 0 85 A A °C 0 Typ 23.0 27.5 24.8 27.3 32.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 6. GTL+ Signal Groups DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage -0.3 VREF -0.2 V 1, See Table 8 VIH Input High Voltage VREF + 0.2 VCCP V 1 VOL Output Low Voltage 0.30 0.60 V 2 VOH Output High Voltage — — V See VTT max in Table 8 IOL Output Low Current 36 48 mA 2 IL Leakage Current ±100 µA 3 IREF Reference Voltage Current ± 15 µA 4 CGTL+ GTL+ Pin Capacitance 8.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 3.14. GTL+ Bus Specifications The GTL+ bus must be routed in a daisy-chain fashion with termination resistors at each end of every signal trace. These termination resistors are placed between the ends of the signal trace and the VTT voltage supply and generally are chosen to approximate the board impedance. The valid high and low levels are determined by the input buffers using a reference voltage called VREF.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 9. Bus Clock AC Specifications T# Parameter Min Max Unit Core Frequency 100 150 150 150 150 166.67 180 200 MHz MHz MHz MHz @ 150 MHz @ 166 MHz @ 180 MHz @ 200 MHz 1 Bus Frequency 50.00 66.67 MHz All Frequencies, 1 15 20 ns 300 ps T1: BCLK Period T2: BCLK Period Stability Figure Figure 13 Notes All Frequencies 2, 3 T3: BCLK High Time 4 ns Figure 13 @>2.0 V, 2 T4: BCLK Low Time 4 ns Figure 13 @<0.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 11. GTL+ Signal Groups AC Specifications T# Parameter Min Max Unit T7A: GTL+ Output Valid Delay H→L 0.55 0.80 4.4 4.4 ns ns Figure 14 @ 150 MHz, 256K L2 All other components 1, 2 T7B: GTL+ Output Valid Delay L→H 0.55 0.80 3.9 3.9 ns ns Figure 14 @ 150 MHz, 256K L2 All other components 1, 2 T8: GTL+ Input Setup Time 2.2 ns Figure 15 3, 4, 5 T9: GTL+ Input Hold Time 0.45 0.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 13. 3.3 V Tolerant Signal Groups AC Specifications T# Parameter Min Max Unit Figure T11: Notes 3.3 V Tolerant Output Valid Delay 1 8 ns Figure 14 1 T12: 3.3 V Tolerant Input Setup Time 5 ns Figure 15 2, 3, 4, 5 T13: 3.3 V Tolerant Input Hold Time 1.5 ns Figure 15 T14: 3.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 14.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 15. APIC Clock and APIC I/O AC Specifications T# Parameter Min Max Unit Figure Notes T21A: PICCLK Frequency 2 33.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 16. Boundary Scan Interface AC Specifications T# Parameter Min Max Unit T30: TCK Frequency T31: TCK Period T32: TCK High Time T33: TCK Low Time T34: TCK Rise Time T35: TCK Fall Time T36: TRST# Pulse Width T37: — 16 MHz 62.5 — ns Figure 13 25 ns Figure 13 @2.0 V, 1 25 ns Figure 13 @0.8 V, 1 5 ns Figure 13 (0.8 V-2.0 V), 1, 2 5 ns Figure 13 (2.0 V-0.
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E Tr Tf Th Tl Tp = = = = = PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Rise Time Fall Time High Time Low Time Period Figure 13. Generic Clock Waveform Tx Tpw V VHI VLO = = = = = Valid Delay Pulse Width 1.0 V for GTL+ signal group; 1.5 V for 3.3 V Tolerant, APIC, and JTAG signal groups GTL+ signals must achieve a DC high level of at least 1.2V GTL+ signals must achieve a DC low level of at most 0.8V Figure 14.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Ts Th V = = = Setup Time Hold Time 1.0 V for GTL+ signal group; 1.5 V for 3.3 V Tolerant, APIC and JTAG signal groups Figure 15. Setup and Hold Timings LAG = T21B (FRC Mode BCLK to PICCLK offset) Figure 16.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 1.5 V Clk Ref τ α 0.3-0.8 V /ns VREF + 0.2 VREF φ −ρ VREF − 0.2 Vstart Clock Tsu +0.05ns Time The Hi to Low Case is analogous. α = Overshoot τ = Minimum Time at High ρ = Amplitude of Ringback φ = Final Settling Voltage Figure 17.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Tt Tu Tv Tw Tx = = = = = Ty = Tz = T9 (GTL+ Input Hold Time) T8 (GTL+ Input Setup Time) T10 (RESET# Pulse Width) T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time).
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E Tr Ts Tu Tv Tw Tx Ty Tz = = = = = = = = PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz T43 (All Non-Test Inputs Setup Time) T44 (All Non-Test Inputs Hold Time) T40 (TDO Float Delay) T37 (TDI, TMS Setup Time) T38 (TDI, TMS Hold Time) T39 (TDO Valid Delay) T41 (All Non-Test Outputs Valid Delay) T42 (All Non-Test Outputs Float Delay) Figure 20. Test Timings (Boundary Scan) Tq = T36 (TRST# Pulse Width) Figure 21. Test Reset Timings 3.16.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 17. Flexible Motherboard (FMB) Power Recommendations1 Symbol Parameter Low End High End Unit Notes VCCP Full FMB Primary VCC Socketed VRM Primary VCC 2.4 3.1 3.5 3.5 V V 5% tolerance over range VCCS FMB Secondary VCC 3.3 3.3 V 5% tolerance VCC5 FMB 5 V VCC 5.0 5.0 V 5% tolerance PMax FMB Thermal Design power 45 W ICCP Full FMB VCCP Current 0.3 14.5 A ICCS FMB VCCS Current 0 3.
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E 4.1. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz System Specification Figure 22 shows a typical system that a GTL+ device would be placed into. The typical system is shown with two terminations and multiple transceiver agents connected to the bus. The receivers have differential inputs connected to a reference voltage, VREF, which is generated externally by a voltage divider. Typically, one voltage divider exists at each component. Here one is shown for the entire network. Figure 22.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 4.1.1. System DC Parameters The following system DC parameters apply to Figure 22. Table 18. System DC Parameters Symbol VTT Parameter Termination Voltage Value Tolerance 1.5 V ±10% Notes VREF Input Reference Voltage 2/3 VTT ±2% 1 RT Termination Resistance ZEFF (nominal) See Note 2, 4 ZEFF Effective (Loaded) Network Impedance 45–65 Ω 2, 3 NOTES: 1. 2. 3.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 19. System Topological Guidelines Parameter Description Maximum Trace Length To meet a specific clock cycle time, the maximum trace length between any two agents must be restricted.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E Table 20. Specifications for Signal Quality Parameter Description Specification Maximum Signal Overshoot/Undershoot Maximum Absolute voltage a signal extends above VTT or below VSS (simulated w/o protection diodes). 0.3 V (guideline) Settling Limit The maximum amount of ringing, at the receiving chip pad, a signal must be limited to before its next transition.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz It is expected that the larger the overshoot α, the smaller the amount of time, τ, needed to maintain setup time to within +0.05 ns of the nominal value. For a given value of α, it is likely that τ will be the longest for the slowest input edge rate of 0.3 V/ns. Furthermore, there may be some dependence between τ and lower starting voltages than VREF – 0.2 V (for Lo-to-Hi transitions) for the reason described later in Section 4.2.3.2.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E V start 1.5 V C lk Ref δ 3 .0 V REF + 0.2 ρ V /n s V REF φ 0. 3 V/ ns V REF- 0.2 α 10 ps rise/fal l Edges τ Clock T su +0.05ns Time Figure 25. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Ringback Tolerance ρ and δ are respectively, the amplitude and duration of square-wave ringback, below the threshold voltage (VREF), that the receiver can tolerate without increasing TSU by more than 0.
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E 4.1.4. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz AC Parameters: Flight Time Signal Propagation Delay is the time between when a signal appears at a driver pin and the time it arrives at a receiver pin. Flight Time is often used interchangeably with Signal Propagation Delay but it is actually quite different.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz If either the rising or falling edge is slower than 0.3V/ns through the overdrive region beyond VREF, (i.e., does not always stay ahead of an 0.3 V/ns line), then the flight time for a rising edge is determined by E extrapolating back from the signal crossing of VREF +200 mV to VREF using an 0.3 V/ns slope as indicated in Figure 27. Figure 27. Flight Time of a Rising Edge Slower Than 0.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Figure 28. Extrapolated Flight Time of a Non-Monotonic Rising Edge Figure 29. Extrapolated Flight Time of a Non-Monotonic Falling Edge The maximum acceptable Flight Time is determined on a net-by-net basis, and is usually different for each unique driver-receiver pair.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Where, TCO-MIN is the minimum clock-to-out delay of the driving agent, THOLD-MIN is the minimum hold time required by the receiver, and TCLK_SKEW-MAX is defined above. The Hold time equation is independent of clock jitter, since data is released by the driver and is required to be held at the receiver on the same clock edge. previous section.
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E 4.2.2. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz I/O Buffer AC Specification Table 22 contains the I/O Buffer DC parameters. Table 22. I/O Buffer AC Parameters Symbol Parameter Min Max Unit Figure Notes dV/dt EDGE Output Signal Edge Rate, rise 0.3 0.8 V/ns 1, 2, 3 dV/dt EDGE Output Signal Edge Rate, fall 0.3 –0.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Since Ref8N is not the worst case network, and is expected to be modeled without many real system effects (e.g., inter-trace crosstalk, DC & AC losses), the required signal quality is slightly different than that specified in Section 4.1.3 of this document.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Figure 30. Acceptable Driver Signal Quality Figure 31.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz THD’ is the receiver’s hold time plus board clock driver and clock distribution skew minus the driver’s on-chip clock phase shift, clock distribution skew, and jitter, plus other data latch or JTAG delays (assuming these driver numbers are not included in the driver circuit simulation, as was done for setup in the above paragraph). Note that THD’ may end up being a negative number, i.e. ahead of the clock, rather than after it.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Figure 33. Clock to Output Data Timing (TCO) TCO measurement for a Lo-to-Hi signal transition is shown in Figure 35. The TCO measurement for Hi-toLo transitions is similar. 4.2.3.2. shaping logic gates, and the edge-triggered (or pulse-triggered) flip-flop. The output of the flipflop must be monitored. 2. The receiver’s Lo-to-Hi setup time should be determined using a nominal input waveform like the one shown in Figure 34 (solid line).
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz and 1.5 V to ‘VREF+200 mV’ for Hi-to-Lo transitions —dashed lines in Figure 34 and Figure 35) do not require TSU to be made longer. This step is needed since a lower starting voltage may cause the input differential amplifier to require more time to switch, due to having been in deeper saturation in the initial state. VIN_LOW_MAX = VREF - 200 mV at the rate of 0.3V/ns. 4. For both the 0.3 V/ns edge rate and faster edge rates (up to 0.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz V start 1.5 V Clk Ref 3.0 V /ns V REF + 0.2 V REF 0 .3 V /n s V REF − 0.2 Clock T su Time Figure 35. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Setup Time Hold time for GTL+ , THOLD, is defined as: 2. The receiver’s Lo-to-Hi hold time should be determined using a nominal input waveform that starts at VIN_LOW_MAX (VREF - 200 mV) and goes to VTT, at a fast edge rate of 0.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 4.2.3.3. Receiver Ringback Tolerance Refer to Section 4.1.3.1 for a complete description of the definitions and methodology for determining receiver ringback tolerance. The time remaining for TCO-MAX and TSU-MIN can be split ~60/40% (recommendation). Therefore, in this example, TCO-MAX would be 4.0 ns, and TSU-MIN 2.8 ns. NOTE 4.2.4. This a numerical example, and does not necessarily apply to any particular device.
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E 4.3. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Package Specification This information is also included for designers of components for a GTL+ bus. The package that the I/O transceiver will be placed into must adhere to two critical parameters. They are package trace length, (the electrical distance from the pin to the die), and package capacitance.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz REF8N Topology: 1.5 volts 42 ohms 0.10 in. 0.9 in. 0.07 in. 0.105 in. 4 pF 1.02 nS/ft. 3.08nS/ft. 2.1nS/ft. 1.4nS/ft. 200 ohms 42 ohms 40 ohms 66 ohms 4 pF 1.02 nS/ft. 3.08nS/ft. 2.1nS/ft. 1.4nS/ft. 200 ohms 42 ohms 40 ohms 66 ohms 0.10 in. 0.9 in. 0.07 in. 1.5 volts 42 ohms 2 pF 1.8 nS/ft. 0.5 in. 72 ohms 2.2 nS/ft. 3.1 in. 72 ohms 0.10 in. 0.9 in. 0.105 in. 4 pF 1.02 nS/ft. 3.08nS/ft. 2.1nS/ft. 1.4nS/ft.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz T5 load2a 0 p6_2 0 Z0=200 TD=8.5ps CCPU_2 p6_2 0 4pf $ Bondwire $ CPU input capacitance T6 line2 0 line3 0 Z0=72 TD=568ps T7 line3 0 load3 0 Z0=50 TD=50ps T8 load3 0 asic_1 0 Z0=75 TD=180PS CASIC_1 asic_1 0 6.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz TX out 0 jim 0 Z0=40 TD=12.25PS ty jim 0 in 0 Z0=66 TD=12.25ps .ENDS 5.0 3.3 V Tolerant Signal Quality Specifications The signals that are 3.3 V tolerant should also meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. There are three signal quality parameters defined for the 3.3 V tolerant signals.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Figure 37. 3.3 V Tolerant Signal Overshoot/Undershoot and Ringback 5.2. RINGBACK SPECIFICATION Ringback refers to the amount of reflection seen after a signal has undergone a transition. The ringback specification is the voltage that the signal rings back to after achieving its farthest excursion. See Figure 37 for an illustration of ringback. Excessive ringback can cause false signal detection or extend the propagation delay.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz higher frequency or otherwise enhanced members of the Pentium Pro processor family. 6.1. Thermal Parameters This section defines the terms used for Pentium Pro processor thermal analysis. E different temperature from the surrounding ambient air, errors could be introduced in the measurements if not handled properly.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 2.66” 1.23” CPU Die L2 Cache Die 2.46” 0.80” A Figure 38. Location of Case Temperature Measurement (Top-side View) A Heat Sink Probe Thermal Interface Material Heat Spreader Ceramic Package Ceramic Package Figure 39. Thermocouple Placement 6.1.3. THERMAL RESISTANCE The thermal resistance value for the case-toambient, ΘCA, is used as a measure of the cooling solution’s thermal performance.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz The parameters are defined by the following relationships where Θ is measured in °C/W (See also Figure 40.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 0.085” 0.130” Height 0.150” 2.235” Figure 41. Analysis Heat Sink Dimensions Table 25 shows the TA required given a 29.2 W processor (150 MHz, 256K cache), and a TC of 85°C.. Table 26 shows the TA required assuming a 40W processor. Table 25 and Table 26 were produced by using the relationships of Section 6.1.3. and the data of Table 24. Table 25. Ambient Temperature Required per Heat Sink Height for 29.2 W and 85°° Case TA vs.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 26. Ambient Temperature Required per Heat Sink Height for 40 W and 85°° Case TA vs. Airflow [Linear Feet per Minute] and Heat Sink Height1 Airflow (LFM): 100 200 400 600 800 1000 With 0.5” Heat Sink 2 — — 3 18 28 33 With 1.0” Heat Sink 2 — 18 41 47 53 54 With 1.5” Heat Sink 2 18 32 49 53 56 58 With 2.0” Heat Sink 2 26 35 50 55 57 59 NOTES: 1. 2. 7.0. At sea level. See Table 24.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Figure 42.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 2.46 ± 0.10" 1.30 ± 0.10" HEAT SPREADER 2.66 ± 0.10" 2.225 ± 0.10" Keep Out Zones 1.025" 0.380" A1 0.195" 0.380" Figure 43. Top View of Keep Out Zones and Heat Spreader Table 27. Pentium® Pro Processor Package Parameter Value Package Type PGA Total Pins 387 Pin Array Modified Staggered Package Size 2.66” x 2.46” (7.76cm x 6.25cm) Heat Spreader Size 2.225” x 1.3” x 0.04” (5.65cm x 3.3cm x 0.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 BC BA AY AW AU AS AQ AN AL AJ AG AF AE AC AB AA Y X W U T S Q P N L K J G F E C B A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 28.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 28.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 28.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 28.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 28.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 29.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 29.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 29.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 29.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 29. Pin Listing in Alphabetic Order (Continued) Signal Name Pin # Signal Name Pin # Signal Name Pin # VSS BA47 VSS BC9 VSS BC39 VSS BC1 VSS BC17 VSS BC41 VSS BC3 VSS BC21 VSS BC43 VSS BC5 VSS BC25 VSS BC45 VSS BC7 VSS BC29 VSS BC47 8.0. 8.1. OVERDRIVE® PROCESSOR SOCKET SPECIFICATION Introduction Intel will offer future OverDrive processors for the Pentium Pro processor.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 8.2.1. VENDOR CONTACTS FOR SOCKET 8 AND HEADER 8 Contact your local Intel representative for a list of participating Socket 8 and Header 8 suppliers. 8.2.2. SOCKET 8 DEFINITION Socket 8 is a 387-pin, modified staggered pin grid array (SPGA), Zero Insertion Force (ZIF) socket.
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E 8.2.2.1. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Socket 8 Pinout Socket 8 is shown in Figure 46 along with the VRM (Header 8) connector. Refer to Section 7.2, for pin listings of the Pentium Pro processor. The OverDrive processor pinout is identical to the Pentium Pro processor pinout. Descriptions of the upgrade specific pins are presented in Table 30. Note the location of pin A1 in relation to the cam shelf position.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 8.2.2.2. Socket 8 Space Requirements The OverDrive processor will be equipped with a fan/heatsink thermal management device. The package envelope dimensions for the OverDrive processor with attached fan/heatsink are shown in Figure 47. Clearance is required around the fan/heatsink to ensure unimpeded air flow for proper cooling (refer to Section 8.5.1.1. for details). Figure 48 shows the Socket 8 space requirements for the OverDrive processor.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 0.1" Heat Sink clip "Keep out Zone" 6 places NOTE: Do Not Interfere with ZIF Handle Operation 0.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz header must not interfere with the installation of the Pentium Pro or OverDrive processors, and must not interfere with the operation of the ZIF socket lever. Alternately, Socket 8, and the installed processor must not interfere with the installation and removal of a VRM in Header 8. NOTE Components placed close to Socket 8 must not impede access to and operation of the handle of the ZIF socket lever.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Pin # Signal Name Pin # Signal Name A1 5Vin B1 5Vin A2 5Vin B2 5Vin A3 5Vin B3 5Vin A4 12Vin B4 12Vin A5 Reserved B5 Reserved A6 Reserved B6 OUTEN A7 VID0 B7 VID1 A8 VID2 B8 VID3 A9 UP# B9 PwrGood A10 VccP B10 Vss A11 Vss B11 VccP A12 VccP B12 Vss A13 Vss B13 VccP A14 VccP B14 Vss A15 Vss B15 VccP A16 VccP B16 Vss A17 Vss B17 VccP A18 VccP B18 Vss A19 Vss B19 VccP A20 Vcc
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz E Table 31. Header 8 Pin Reference Pin Name I/O Usage 12 VIN Input Required +12V±5% Supply 5 VIN Input Required +5V±5% Supply 1 VSS Input Required Ground Reference OUTEN Input Optional When driven high this input will enable the OEM VRM output and float the OverDrive® VRM output. When this input is driven low, the output of the OEM module will float and the OverDrive VRM output will be enabled.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 0.80 Max Component Height on front of VRM PCB 0.14 Max Component Height on back of VRM PCB 2.4 Total height from motherboard to an immovable object 1.8 Total space for VRM / Header 8 from motherboard 0.550 MIN 3.10 Max VRM PCB Width AAAAA AAAA AAAAA AAAAA A AAAAA AAAA AAAAA AAAAA A AAAAA OverDrive R VRM PCB HEADER 8 0.550 REF Minimum distance to VRM components from motherboard 0.090 REF 3.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz + 5 Volt + 5 Volt 10 k Ω Header 8 UP# 10 k Ω Header 8 Socket 8 UP# Socket 8 On-Board VR Figure 51. Upgrade Presence Detect Schematic—Case 1 • 86 Case 2: Header 8 AND alternate voltage source if the system is designed with alternate voltage source and a Header 8 for future upgrade support, then the UP# signal must be connected between Socket 8, Header 8, and the alternate voltage source.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 32. OverDrive® Processor CPUID On-Board VR Type [13:12] Family [11:8] Model [7:4] Stepping [3:0] 1 6 3 X VID3-VID0 4 Socket 8 8.3.3.2. Figure 53. Upgrade Presence Detect Schematic—Case 3 8.3.3. BIOS CONSIDERATIONS Please refer to the Pentium® Pro Processor Developers Manual: Volume 3, Programmer's Reference Manual (Order Number 242691) for BIOS requirements.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz ZIF socket electrical parameters may differ from LIF socket parameters; therefore, be sure to use the appropriate ZIF socket parameters for electrical design simulations. 8.4.1. OverDrive® Processor DC Specifications 8.4.1.1. NOTE DC SPECIFICATIONS Table 33 lists the DC specifications for the OverDrive processor that are either different from or in addition to the Pentium Pro processor specifications. OverDrive® VRM DC Specifications 8.4.1.2.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 34. OverDrive® VRM Specifications Symbol Parameter Min Max Unit Notes VIL Control Signal Input Low Voltage -0.3 0.8 V VIH Control Signal Input High Voltage 2.0 VCC5+0.3 V VOL Control Signal Output Low Voltage 0.4V V VOH5 Control Signal Output High Voltage 2.4 VCC5+0.3 V PWRGOOD ICC5 5.0 V Power Supply Current (VRM input current) 0.100 7.0 7.8 8.7 A A A 1 2 3 ICC12 12.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 8.5. Thermal Specifications This section describes the cooling solution utilized by the OverDrive processor and the cooling requirements for both the processor and VRM. Heat dissipation by the OverDrive processor will be no greater than the Pentium Pro processor, as described in Section 6 and Table 5. 8.5.1. OverDrive ® PROCESSOR COOLING REQUIREMENTS The OverDrive processor will be cooled with a fan/heatsink cooling solution.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 35. OverDrive VRM Power Dissipation for Thermal Design Parameter Typ 1 Max 1 Unit 6.0 6.5 7.0 7.0 7.8 8.7 W W W 2 3 4 105 °C Voltage Regulator Maximum Case Temperature OverDrive VRM Power Dissipation TC, Max Notes NOTES: Specification for the OverDrive® Voltage Regulator Module. A Pentium® Pro processor OEM Module is specific to the design and may differ.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 8.6.1. RELATED DOCUMENTS connections, signal timing and quality, and voltage transients. All references to related documents within this section imply the latest published revision of the related document, unless specifically stated otherwise. Contact your local Intel Sales representative for latest revisions of the related documents.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 38. Electrical Test Criteria for Systems Not Employing Header 8 Criteria VCCP Primary CPU VCC Voltage Refer To: Table 33 including note 4 Comment Measured Under the following Loading Conditions: Max ICCP at Steady-State Min ICCP at Steady-State Fast Switch between Max and Min ICCP Refer to Table 33 for OverDrive® processor ICCP specification. Table 39.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 8.6.3.2. Pentium® Pro Processor Cooling Requirements (Systems Testing Only) The Pentium Pro processor case temperature must meet the specifications of the Pentium Pro processor. Thermal testing should be performed under worst case thermal loading (Refer to 8.6.3.1. for loading description), and with a cooling solution representative of the OEM’s cooling solution. E Refer to Table 5 for the Pentium Pro processor case temperature specification. 8.6.3.3.
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E 8.6.4.2. PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz OverDrive® VRM Clearance and Airspace Requirements boot properly without error messages when the OverDrive processor is installed. Refer to Figure 50 for a drawing of the various clearance and airspace requirements of the OverDrive VRM. Nothing must intrude into the space envelope, including airspace region, defined in Figure 50 with the exception of Header 8 itself. 8.6.5. 8.6.5.1.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz 8.6.6.3. Jumper Configuration 8.6.6.5. Documentation E End user configured jumpers are not recommended. If design requires jumpers or switches to upgrade the system, a detailed jumper description in the manual is required. The jumpers must be easy to locate and set. Jumper identification should be silk-screened on the motherboard if possible. Jumper tables on the inside of the system case are recommended.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz APPENDIX A This appendix provides an alphabetical listing of all Pentium Pro processor signals. Pins that do not appear here are not considered bus signals and are described in Table 2. A.1 Ab[23:16]#/DID[7:0]# signals. Pentium Pro processor bus agents that support deferred replies sample the deferred ID and perform an internal match against any outstanding transactions waiting for deferred replies.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Snoop requests and cache-line writeback transactions are unaffected by A20M# input. Address 20 is not masked when the processor samples external addresses to perform internal snooping. than the maximum number of entries defined by the power-on configuration (1 or 8), the Request Phase is not being stalled by an active BNR# sequence and the ADS# associated with the previous Request Phase is sampled inactive.
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E A.4 PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz AERR# (I/O) The AERR# signal is the address parity error signal. Assuming the AERR# driver is enabled during the power-on configuration, a bus agent can drive AERR# active for exactly one clock during the Error Phase of a transaction. AERR# must be inactive for a minimum of two clocks. The Error Phase is always three clocks from the beginning of the Request Phase.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz when ASZ[1:0]# equals 00. All observing bus agents that support the 64GByte (36- bit) address space must respond to the transaction when ASZ[1:0]# equals 00B or 01B. A.7 ATTR[7:0]# (I/O) The ATTR[7:0]# signals are the attribute signals. They are driven by the request initiator during the second Request Phase clock on the Ab[31:24]# pins. The ATTR[7:0]# signals are valid for all transactions. The ATTR[7:3]# are reserved and undefined.
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E A.10 PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz BERR# (I/O) The BERR# signal is the Error group Bus Error signal. It is asserted to indicate an unrecoverable error without a bus protocol violation. The BERR# protocol is as follows: If an agent detects an unrecoverable error for which BERR# is a valid error response and BERR# is sampled inactive, it asserts BERR# for three clocks. An agent can assert BERR# only after observing that the signal is inactive.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz mechanism enables independent control on every new request generation. If BNR# is deasserted on two consecutive sampling points, new requests can be freely generated on the bus. After receiving a new transaction, a bus agent can require an address stall due to an anticipated transaction-queue overflow condition. In response, the bus agent can assert BNR#, three clocks from active ADS# assertion and create a bus stall.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 48. BR[3:0]# Signals Rotating Interconnect Bus Signal Agent 0 Pins Agent 1 Pins Agent 2Pins Agent 3 Pins BREQ0# BR0# BR3# BR2# BR1# BREQ1# BR1# BR0# BR3# BR2# BREQ2# BR2# BR1# BR0# BR3# BREQ3# BR3# BR2# BR1# BR0# During power-up configuration, the central agent must assert the BR0# bus signal. All symmetric agents sample their BR[3:0]# pins on active-toinactive transition of RESET#.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz require four data transfer clocks with valid data on all eight bytes. Partial transfers require one data transfer clock with valid data on the byte(s) indicated by active byte enables BE[7:0]#. Data signals not valid for a particular transfer must still have correct ECC (if data bus ECC is selected). If BE0# is asserted, D[7:0]# transfers the least significant byte. If BE7# is asserted, D[63:56]# transfers the most significant byte.
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E A.21 PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz DEN# (I/0) The DEN# signal is the defer-enable signal. It is driven to the bus on the second clock of the Request Phase on the EXF1#/Ab4# pin. DEN# is asserted to indicate that the transaction can be deferred by the responding agent. A.22 DEP[7:0]# (I/O) The DEP[7:0]# signals are the data bus ECC protection signals. They are driven during the Data Phase by the agent responsible for driving D[63:0]#.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz capability of the requesting agent. For the Pentium Pro processor, DSZ#= 00, always. A.26 EXF[4:0]# (I/O) by the request initiator during the second clock of the Request Phase. The signals specify any special functional requirement associated with the transaction based on the requester mode or capability. The signals are defined in Table 51.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz completes, the Pentium Pro processor de-asserts FRCERR if BIST completed successfully and continues to assert FRCERR if BIST fails. If the Pentium Pro processor does not execute the BIST action, then it keeps FRCERR asserted for approximately 20 clocks and then de-asserts it. The Pentium® Pro Processor Developer’s Manual, Volume 1: Specifications (Order Number 242690) describes how a Pentium Pro processor can be configured as a master or a checker.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz A.33 INIT# (I) The INIT# signal is the Execution Control group initialization signal. Active INIT# input resets integer registers inside all Pentium Pro processors without affecting their internal (L1 or L2) caches or their floating-point registers. Each Pentium Pro processor begins execution at the power-on reset vector configured during power-on configuration regardless of whether INIT# has gone inactive.
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E A.37 PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz LOCK# (I/O) The LOCK# signal is the Arbitration group bus lock signal. For a locked sequence of transactions, LOCK# is asserted from the first transaction’s Request Phase through the last transaction’s Response Phase. A locked operation can be prematurely aborted (and LOCK# deasserted) if AERR# or DEFER# is asserted during the first bus transaction of the sequence.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 53.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Unless its outputs are tristated during power-on configuration, after active-to-inactive transition of RESET#, the Pentium Pro processor optionally executes its built-in self-test (BIST) and begins program execution at reset-vector 0_000F_FFF0H or 0_FFFF_FFF0H. A.44 RP# (I/O) The RP# signal is the Request Parity signal. It is driven by the request initiator in both clocks of the Request Phase. RP# provides parity protection on ADS# and REQ[4:0]#.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz Table 54. Transaction Response Encodings RS[2:0] • • Description DEFER# N/A N/A 000 Idle State. 001 Retry Response. The transaction is canceled and must be retried by the initiator. 0 1 010 Defer Response. The transaction is suspended. The defer agent will complete it with a defer reply 0 1 011 Reserved. 0 1 100 Hard Failure. The transaction received a hard error. Exception handling is required.
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E PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz of the Request Phase on the EXF4#/Ab7# signal. It is asserted by the Pentium Pro processor to indicate that the processor is in System Management Mode and is executing out of SMRAM space. A.49 SPLCK# (I/O) The SPLCK# signal is the Split Lock signal. It is driven in the second clock of the Request Phase on the EXF3#/Ab6# signal of the first transaction of a locked operation.
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PENTIUM® PRO PROCESSOR AT 150, 166, 180, and 200 MHz • • E If the transaction also has a request initiated transfer, that the request initiated TRDY# was asserted and then deasserted (TRDY# must be deasserted for at least one clock between the TRDY# for the write and the TRDY# for the implicit writeback), • DBSY# is observed inactive on the clock TRDY# is asserted.