Specifications

DL06 Micro PLC User Manual, 3rd Edition, Rev. C
E–76
Appendix E: High-speed Input and Pulse Output Features
1
2
3
4
E
6
7
8
9
10
11
12
13
14
A
B
C
D
Mode 60: Discrete Inputs with Filter
Purpose
The last mode we will discuss for the HSIO circuit is Mode 60, Discrete Inputs with Filter.
The purpose of this mode is to allow the input circuit to reject narrow pulses and accept wide
ones, as viewed from the ladder program. This is useful in especially noisy environments or
other applications where pulse width is important. In all other modes in this appendix, X0 to
X3 usually support the mode functions as special inputs. Only spare inputs operate as filtered
inputs by default. Now in Mode 60, all four inputs X0 through X3 function only as discrete
filtered inputs.
Functional Block Diagram
Refer to the block diagram below. When the lower byte of HSIO Mode register V7633
contains a BCD “60”, the input filter in the HSIO circuit is enabled. Each input X0 through
X3 has its own filter time constant. The filter circuit assigns the outputs of the filters as logical
references X0 through X3.
Input Filter Timing Parameters
Signal pulses at inputs X0 – X3 are filtered by using a delay time. In the figure below, the
input pulse on the top line is longer than the filter time. The resultant logical input to ladder
is phase-shifted (delayed) by the filter time on both rising and falling edges. In the bottom
waveforms, the physical input pulse width is smaller than the filter time. In this case, the
logical input to the ladder program remains in the OFF state (input pulse was filtered out).
Input Circuit
PLC
DL06
X0
Y0, Y1
X4-X23
Y2-Y17
V-memory
V7633 0060
Mode select
I/O data
HSIO
FILTERS
X0-X3
X1 X2
Output Circuit
CPU
X3
Time
Physical Input
X0
Filter T
ime
Logical Input
X0
Physical Input
X0
Logical Input
X0
Filter Time