Specifications

DL06 Micro PLC User Manual, 3rd Edition, Rev. C
E–72
Appendix E: High-speed Input and Pulse Output Features
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E
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A
B
C
D
Mode 50: Pulse Catch Input
Purpose
The HSIO circuit has a pulse-catch mode of operation. It monitors the signal on inputs X0 -
X3, preserving the occurrence of a narrow pulse. The purpose of the pulse catch mode is to
enable the ladder program to see an input pulse which is shorter in duration than the current
scan time. The HSIO circuit latches the input event on input X0 - X3 for one scan. This
contact automatically goes off after one scan.
Functional Block Diagram
Refer to the block diagram below. When the lower byte of HSIO Mode register V7633
contains a BCD “50”, the pulse catch mode in the HSIO circuit is enabled. X0 - X3
automatically become the pulse catch inputs, which set the latch on each rising edge. The
HSIO resets the latch at the end of the next CPU scan. Inputs X1 X2, and X3 can be filtered
discrete inputs, also.
Pulse Catch Timing Parameters
Signal pulses at X0 - X3 must meet certain timing criteria to guarantee a pulse capture will
result. Refer to the timing diagram below. The input characteristics of X0 are fixed (it is not a
programmable filtered input). The minimum pulse width is 0.1 ms. There must be some
delay before the next pulse arrives, such that the pulse period cannot be smaller than 0.5 ms.
If the pulse period is smaller than 0.5 ms, the next pulse will be considered part of the current
pulse.
NOTE: The pulse catch and filtered input functions are opposite in nature. The pulse catch feature
seeks to capture narrow pulses, while the filter input feature seeks to reject narrow pulses.
Time
Pulse
Input
X0
0.1 ms minimum
0.5 ms minimum
Input Circuit
CPU
PLC
DL06
X0
Y0, Y1
X4 - X23
Y2 -Y17
V-memory
V7633 0050
Mode select
I/O data
HSIO
Latch
Set Reset
X1, X2, X3
scan
Filter
Output Circuit
Latch
or