Specifications

Mode 10: High-Speed Counter
Purpose
The HSIO circuit contains two high-speed counters. A single pulse train from an external
source (X0) clocks the counter on each signal leading edge. The counter counts only upwards,
from 0 to 99999999. The counter compares the current count with up to 24 preset values,
which you define. The purpose of the presets is to quickly cause an action upon arrival at
specific counts, making it ideal for such applications as cut-to-length. It uses counter registers
CT174 to CT177 in the CPU.
Functional Block Diagram
Refer to the block diagram below. When the lower byte of HSIO Mode register V7633
contains a BCD “10”, the high-speed up counter in the HSIO circuit is enabled. X0 and X1
automatically become the “clock” inputs for the high-speed counters, incrementing them
upon each off-to-on transition. The external reset input on X2 and X3 are the default
configuration for Mode 10.
Instead of using X2 and X3 as dedicated reset inputs, you can configure X2 and X3 as normal
filtered inputs. In this way, the counter reset must be generated in ladder logic.
DL06 Micro PLC User Manual, 3rd Edition, Rev. C
E–7
Appendix E: High-speed Input and Pulse Output Features
1
2
3
4
E
6
7
8
9
10
11
12
13
14
A
B
C
D
Input Circuit
CPU
PLC
DL06
Y0 - Y1
X4 - X23
Y2 - Y17
V-memory
V7633
0010
Mode Select
I/O data
HSIO
Counter 1
CLK
Reset
X0 X1
Output Circuit
X2 - X3
Counter 2
CLK Reset
Filter
Input Circuit
CPU
PLC
DL06
Y0 - Y1
X4 - X23
Y2 - Y17
V-memory
V7633
0010
Mode Select
I/O data
HSIO
Counter 1
CLK
Reset
X0 X2 X1
Output Circuit
X3
Counter 2
CLK Reset
Filter