Specifications

Mode 40: High-Speed Interrupts
Purpose
The HSIO Mode 40 provides a high-speed interrupt to the ladder program. This capability is
provided for your choice of the following application scenarios:
• External events need to trigger an interrupt subroutine in the CPU. Using immediate I/O
instructions in the subroutine is typical.
• An interrupt routine needs to occur on a timed basis which is different from the CPU scan time
(either faster or slower). The timed interrupt is programmable, from 5 to 999 mS.
Functional Block Diagram
The HSIO circuit creates the high-speed interrupt to the CPU. The following diagram shows
the external interrupt option, which uses X0. In this configuration X1, X2 and X3 are
external interrupts or normal filtered inputs.
Alternately, you may configure the HSIO circuit to generate interrupts based on a timer, as
shown below. In this configuration, inputs X0 is a filtered input.
DL06 Micro PLC User Manual, 3rd Edition, Rev. C
E–67
Appendix E: High-speed Input and Pulse Output Features
1
2
3
4
E
6
7
8
9
10
11
12
13
14
A
B
C
D
Input Circuit
CPU
PLC
DL06
Y0, Y1
X4 - X23
Y2 - Y17
V-memory
V7633 0040
Mode select
I/O data
X0
Interrupt
Output Circuit
X1, X2, X3
HSIO
Filter
Interrupt
or
Filter
Interrupt
Timer
Input Circuit
CPU
PLC
DL06
X0
Y0, Y1
X4 - X23
Y2 -Y17
V-memory
V7633 0040
Mode select
I/O data
HSIO
Interrupt
X1, X2, X3
Interrupt
Output Circuit
Filter
Interrupt
or