Specifications

Dedicated High- Speed I/O Circuit
The internal CPU’s main task is to execute the ladder program and read/write all I/O points
during each scan. In order to service high-speed I/O events, the DL06 includes a special
circuit which is dedicated to a portion of the I/O points. Refer to the DL06 block diagram in
the figure below.
The high-speed I/O circuit (HSIO) is dedicated to the first four inputs (X0 – X3) and the
first two outputs (Y0 – Y1). We might think of this as a CPU helper. In the default operation
(called “Mode 60”) the HSIO circuit just passes through the I/O signals to or from the CPU,
so that all twenty inputs behave equally and all sixteen outputs behave equally. When the
CPU is configured in any other HSIO Mode, the HSIO circuit imposes a specialized
function on the portion of inputs and outputs shown. The HSIO circuit operates
independently of the CPU program scan. This provides accurate measurement and capturing of
high-speed I/O activity while the CPU is busy with ladder program execution.
Wiring Diagrams for Each HSIO Mode
After choosing the appropriate HSIO mode for your application, you’ll need to refer to the
section in this appendix for that specific mode. Each section includes wiring diagrams to help
you connect the High-Speed I/O points correctly to field devices. An example of a High
Speed Counter mode diagram is shown below.
DL06 Micro PLC User Manual, 3rd Edition, Rev. C
E–3
Appendix E: High-speed Input and Pulse Output Features
1
2
3
4
E
6
7
8
9
10
11
12
13
14
A
B
C
D
Output Circuit
Input Circuit
CPU
20 Discrete Inputs
16 Discrete Outputs
PLC
DL06
High-Speed
I/O Circuit
X0 - X3
Y
0, Y1
X4 - X23
Y
2 - Y17
Counter Input Wiring
Signal Common
Signal
+–
12-24 VDC Supply
L
O
G
I
C
K
o
y
o
0
6
C0 C4C2X1X3 X4 X6 X11X13 X14 X16 X21X23 N.C.
C1 C3X2 X5 X7 X10 X12
X15 X17 X20 X22X0
N.C.
AC
(
N
)
24V
0V
N.C.
C1 C3Y0 Y15Y12Y10 Y17Y7Y5Y2
C0 C2 Y16Y14Y13Y11Y6Y4Y3Y1
LGG
AC
(
L
)
D0-06DR
2.0AOUTPUT: 6-240V 50 - 60Hz 2.0A, 6 - 27V
INPUT: 12 - 24V 3 - 15mA
Y
X
40VA50-60HzPWR: 100-240V
0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 21 22
23
PORT1 PORT2
TERM
RUN STOP
P
WR
R
UN
C
PU
T
X1
RX1
T
X2
R
X2