Specifications

Mode 10: High-Speed Counter
Purpose
The HSIO circuit contains one high-speed counter. A single pulse train from an external
source (X0) clocks the counter on each signal leading edge. The counter counts only upwards,
from 0 to 99999999. The counter compares the current count with up to 24 preset values,
which you define. The purpose of the presets is to quickly cause an action upon arrival at
specific counts, making it ideal for such applications as cut-to-length. It uses counter registers
CT76 and CT77 in the CPU.
Functional Block Diagram
Refer to the block diagram below. When the lower byte of HSIO Mode register V7633
contains a BCD “10”, the high-speed up counter in the HSIO circuit is enabled. X0
automatically becomes the “clock” input for the high-speed counter, incrementing it upon
each off-to-on transition. The external reset input on X2 is the default configuration for
Mode 10. Input X1 is the filtered input, available to the ladder program.
Instead of using X2 as a dedicated reset input, you can configure X2 as a normal filtered
input. In this way, the counter reset must be generated in ladder logic.
Next, we will discuss how to program the high-speed counter and its presets.
DL05 Micro PLC User Manual, 6th Edition, Rev. C
E–6
Appendix E: High-speed Input and Pulse Output Features
1
2
3
D
E
6
7
8
9
10
11
1
1
14
A
B
C
D
Input Circuit
CPU
PLC
DL05
X0
Y0 - Y1
X3-X7
Y2 - Y5
V-memory
V7633 0010
Mode Select
I/O data
HSIO
COUNTER
CLK
Reset
X1-X2
FILTER
Output Circuit
Input Circuit
CPU
PLC
DL05
X0
Y0 - Y1
X3 - X7
Y2 - Y5
V-memory
V7633
0010
Mode Select
I/O data
HSIO
COUNTER
CLK
Reset
X2 X1
FILTER
Output Circuit