Datasheet

Product Errata 15
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.16 February 2008
278 Incorrect Memory Controller Operation In Ganged Mode X
279 HyperTransport™ Link RTT and RON Specification
Violations
X
280 Time Stamp Counter May Yield An Incorrect Value X X
293 Memory Instability After PWROK Assertion X X
295 DRAM Phy Configuration Access Failures X
297 Single Machine Check Error May Report Overflow No fix planned.
298 L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit
XX
300 Hardware Memory Clear Is Not Supported After Software
DRAM Initialization
XX
301 Performance Counters Do Not Accurately Count MFENCE
or SFENCE Instructions
XX
302 MWAIT Power Savings May Not Be Realized when Two or
More Cores Monitor the Same Address
XX
308 Processor Stall in C1 Low Power State X X
309 Processor Core May Execute Incorrect Instructions on
Concurrent L2 and Northbridge Response
XX
312 CVTSD2SS and CVTPD2PS Instructions May Not Round
to Zero
No fix planned.
315 FST and FSTP Instructions May Calculate Operand
Address in Incorrect Mode
XX
319 Inaccurate Temperature Measurement X X
Table 9. Cross-Reference of Product Revision to Errata (Continued)
No. Errata Description
Revision
Number
DR-BA DR-B2