Datasheet
14 Product Errata
41322 Rev. 3.16 February 2008
Revision Guide for AMD Family 10h Processors
Product Errata
This section documents product errata for the processors. A unique tracking number for each erratum
has been assigned within this document for user convenience in tracking the errata within specific
revision levels. Table 9 cross-references the revisions of the part to each erratum. An “X” indicates
that the erratum applies to the revision. The absence of an “X” indicates that the erratum does not
apply to the revision. An “*” indicates advance information that the erratum has been fixed but not yet
verified. “No fix planned” indicates that no fix is planned for current or future revisions of the
processor.
Note: There may be missing errata numbers. Errata that have been resolved from early revisions of
the processor have been deleted, and errata that have been reconsidered may have been
deleted or renumbered.
Table 9. Cross-Reference of Product Revision to Errata
No. Errata Description
Revision
Number
DR-BA DR-B2
57 Some Data Cache Tag Eviction Errors Are Reported As
Snoop Errors
No fix planned.
60 Single Machine Check Error May Report Overflow
No fix planned.
77 Long Mode CALLF or JMPF May Fail To Signal GP When
Callgate Descriptor is Beyond GDT/LDT Limit
No fix planned.
178 Default RdPtrInit Value Does Not Provide Sufficient Timing
Margin
XX
244 A DIV Instruction Followed Closely By Other Divide
Instructions May Yield Incorrect Results
XX
246 Breakpoint Due to An Instruction That Has an Interrupt
Shadow May Be Delivered to the Hypervisor
XX
248 INVLPGA of A Guest Page May Not Invalidate Splintered
Pages
X
254 Internal Resource Livelock Involving Cached TLB Reload X X
260 REP MOVS Instruction May Corrupt Source Address X X
261 Processor May Stall Entering Stop-Grant Due to Pending
Data Cache Scrub
No fix planned.
263 Incompatibility With Some DIMMs Due to DQS Duty Cycle
Distortion
No fix planned
264 Incorrect DRAM Data Masks Asserted When DRAM
Controller Data Interleaving Is Enabled
XX
269 ITT Specification Exceeded During Power-Up Sequencing No fix planned.
273 Lane Select Function Is Not Available for Link BIST on 8-
Bit HyperTransport™ Links In Ganged Mode
XX
274 IDDIO Specification Exceeded During Power-Up
Sequencing
X