Revision Guide for AMD Family 10h Processors Publication # 41322 Revision: 3.
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41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors Revision History Date Revision Description February 2008 3.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors The purpose of the Revision Guide for AMD Family 10h Processors is to communicate updated product information to designers of computer systems and software developers.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors Processor Identification This section shows how to determine the processor revision, program and display the processor name string, and construct the processor name string. Revision Determination Figure 1 shows the format of the value returned in EAX by CPUID Function 1. Figure 1.
Revision Guide for AMD Family 10h Processors Table 2. 41322 Rev. 3.16 February 2008 Supported Mixed Silicon Revision Configurations Silicon Revison DR-BA DR-B2 DR-BA YES YES DR-B2 YES YES Refer to Table 1 on page 5 for CPUID values for these revisions. Errata workarounds must be applied according to revision as described in the Product Errata section starting on page 14 unless otherwise noted in the workraound of an erratum.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors Programming and Displaying the Processor Name String This section, intended for BIOS programmers, describes how to program and display the 48-character processor name string that is returned by CPUID Fn8000_000[4:2].
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors • PkgTyp[3:0] is from CPUID Fn8000_0001_EBX. This field specifies the package type as defined in the BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 10h Processors, order #31116, and is used to index the appropriate string tables from Table 3. • NC[7:0] is from CPUID Fn8000_0008[ECX].
41322 Rev. 3.16 February 2008 Table 4.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors Table 6. String1 Values for Socket AM2r2 Processors Pg[0] NC [7:0] String [3:0] 0b 03h 2h All other values Table 7.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors F4x164 Fixed Errata Register Communicating the status of an erratum requiring a workaround within a stepping of a processor family is necessary in certain circumstances. F4x164 is used to communicate the status of such an erratum fix so that BIOS or system software can determine the necessity of applying the workaround.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length) This register, as defined in AMD64 Architecture Programmer’s Manual Volume 2: System Programming, order# 24593, is used to specify the number valid status bits within the OS Visible Work-around status registers. The default value of this register is 0000_0000_0000_0000h. BIOS shall program the specified length as specified in Table 8 prior to hand-off to the OS.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status) This register, as defined in AMD64 Architecture Programmer’s Manual Volume 2: System Programming, order# 24593, provides the status of the known OS visible errata. Known errata are assigned an OSVW_ID corresponding to the bit position with in the valid status field. Operating system software should use MSRC001_0140 to determine the valid length of the bit status field.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors Product Errata This section documents product errata for the processors. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. Table 9 cross-references the revisions of the part to each erratum. An “X” indicates that the erratum applies to the revision.
41322 Rev. 3.16 February 2008 Table 9. No.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 Table 10 cross-references the errata to each processor segment. An empty cell signifies that the erratum does not apply to the processor segment. “X” signifies that the erratum applies to the processor segment. “N/A” signifies that the erratum does not apply to the processor segment due to the silicon revision.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors Table 11 cross-references the errata to each package type. An empty cell signifies that the erratum does not apply to the package type. “X” signifies that the erratum applies to the package type. “N/A” signifies that the erratum does not apply to the package type due to the silicon revision. Socket AM2r2 Errata Number Cross-Reference of Errata to Package Type Socket Fr2 (1207) Table 11.
Revision Guide for AMD Family 10h Processors 57 41322 Rev. 3.16 February 2008 Some Data Cache Tag Eviction Errors Are Reported As Snoop Errors Description In some cases, the machine check error code on a data cache (DC) tag array parity error erroneously classifies an eviction error as a snoop error. The common cases of cache line replacements and external probes are classified correctly (as eviction and snoop respectively).
41322 Rev. 3.16 February 2008 60 Revision Guide for AMD Family 10h Processors Single Machine Check Error May Report Overflow Description A single parity error encountered in the data cache tag array may incorrectly report the detection of multiple errors, as indicated by the overflow bit of the DC Machine Check Status register (bit 62 of MSR 0x401). Potential Effect on System System software may be informed of a machine check overflow when only a single error was actually encountered.
Revision Guide for AMD Family 10h Processors 77 41322 Rev. 3.16 February 2008 Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor is Beyond GDT/LDT Limit Description If the target selector of a far call or far jump (CALLF or JMPF) instruction references a 16-byte long mode system descriptor where any of the last 8 bytes are beyond the GDT or LDT limit, the processor fails to report a General Protection fault.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 178 Default RdPtrInit Value Does Not Provide Sufficient Timing Margin Description Insufficient separation of the read pointer and write pointer in the synchronization FIFO can lead to setup violations in the transmit FIFO. Potential Effect on System The setup violations may lead to data corruption. Suggested Workaround BIOS should program F2x[1, 0]78[3:0] (RdPtrInit) to 4’h5.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 244 A DIV Instruction Followed Closely By Other Divide Instructions May Yield Incorrect Results Description A DIV instruction with a divisor less than 64 that is followed in close proximity by a DIV, IDIV, or AAM instruction may produce incorrect results. Potential Effect on System Possible data corruption. Suggested Workaround Contact your AMD representative for information on a BIOS update.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 248 INVLPGA of A Guest Page May Not Invalidate Splintered Pages Description When an address mapped by a guest uses a larger page size than the host, the TLB entry created uses the size of the smaller page; this is referred to as page splintering. TLB entries that are the result of page splintering may not be invalidated when the large page is invalidated in the guest using INVLPGA.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 254 Internal Resource Livelock Involving Cached TLB Reload Description Under a highly specific and detailed set of conditions, an internal resource livelock may occur between a TLB reload and other cached operations. Potential Effect on System The system may hang. Suggested Workaround BIOS should set MSR C001_1023h[21] to 1b.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 260 REP MOVS Instruction May Corrupt Source Address Description The processor may corrupt the source address for REP MOVS instructions using 16- or 32-bit addressing when a fault occurs on the first iteration and ECX is greater than 255 and EDI equals 0. Potential Effect on System Unpredictable system behavior. Suggested Workaround Contact your AMD representative for information on a BIOS update.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 261 Processor May Stall Entering Stop-Grant Due to Pending Data Cache Scrub Description The processor may stall if a correctable error is identified by the data cache scrubber within a small window of time before the processor enters a stop-grant state when another scrub is pending. Potential Effect on System The system may hang. Suggested Workaround BIOS should set MSRC001_1022[24]. Fix Planned No fix planned.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 263 Incompatibility With Some DIMMs Due to DQS Duty Cycle Distortion Description Some DDR2 DIMMs exhibit a duty cycle distortion on the first DQS pulse of an incoming read request which may cause the processor's DDR interface to miss a beat of data in a read burst. Potential Effect on System Undefined system behavior due to incorrect read data.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 264 Incorrect DRAM Data Masks Asserted When DRAM Controller Data Interleaving Is Enabled Description The processor may incorrectly assert the DRAM data masks for writes less than a cacheline when DRAM controller data interleaving is enabled. Potential Effect on System Data corruption. Suggested Workaround BIOS should set MSRC001_001F[36] (DisDatMsk) to 1b when F2x110[5] (DctDatIntLv) is set to 1b. Fix Planned Yes.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 269 ITT Specification Exceeded During Power-Up Sequencing Description Processor current consumption may exceed the ITT maximum specified for C0/S0 operation if the VTT voltage regulator is enabled before the VDDIO voltage regulator and the VDDIO regulator enables a low resistance path to VSS while VTT - VDDIO > 400 mV. Potential Effect on System The VTT voltage regulator may shut down if ITT exceeds the platform design limit.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 274 IDDIO Specification Exceeded During Power-Up Sequencing Description Processor current consumption may exceed the IDDIO maximum specified for C0/S0 operation during power-up sequencing. Potential Effect on System None expected if the VDDIO voltage regulator is sourced by a RUN (running) plane from the power supply during power-up sequencing.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 278 Incorrect Memory Controller Operation In Ganged Mode Description The DRAM controller 0 (DCT0) and DRAM controller 1 (DCT1) refresh counters may not be initialized to the same value using hardware controlled DRAM initialization when operating in ganged mode. Potential Effect on System Incorrect memory controller operation.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 279 HyperTransport™ Link RTT and RON Specification Violations Description The RTT and RON specifications for the HyperTransport™ link may be violated on some processor revisions. Potential Effect on System These violations do not result in any other HyperTransport™ link electrical specification violations. There are no known functional failures related to this problem. Suggested Workaround None required. Fix Planned Yes.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 280 Time Stamp Counter May Yield An Incorrect Value Description Reads of the time stamp counter may yield an inconsistent result. Potential Effect on System Undefined behavior for software that relies on a continuously increasing time stamp counter value. Suggested Workaround Contact your AMD representative for information on a BIOS upgrade. Fix Planned Yes.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 293 Memory Instability After PWROK Assertion Description After PWROK is asserted, the DRAM DQS DLL may not lock properly. Potential Effect on System The system may have degraded memory margins leading to unreliable DRAM signaling. In some circumstances, this may cause BIOS to degrade the memory speed.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 295 DRAM Phy Configuration Access Failures Description Under a highly specific set of asynchronous timing conditions established during cold boot (S5 to S0 transition) or resume (S4 or S3 to S0 transition), the skew between the DRAM controllers (DCTs) and DRAM phy may lead to unreliable communication for DRAM phy configuration accesses.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 297 Single Machine Check Error May Report Overflow Description A single tag snoop parity error encountered in the instruction cache tag array may incorrectly report the detection of multiple errors, as indicated by the overflow bit of the IC Machine Check Status register (MSR 0000_0405[62]). Potential Effect on System System software may be informed of a machine check overflow when only a single error was actually encountered.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 298 L2 Eviction May Occur During Processor Operation To Set Accessed or Dirty Bit Description The processor operation to change the accessed or dirty bits of a page translation table entry in the L2 from 0b to 1b may not be atomic. A small window of time exists where other cached operations may cause the stale page translation table entry to be installed in the L3 before the modified copy is returned to the L2.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 300 Hardware Memory Clear Is Not Supported After Software DRAM Initialization Description When using software-controlled DRAM device initialization through EnDramInit (F2x[1, 0]7C DRAM Initialization Register[31]), hardware memory clear using MemClrInit (F2x110 DRAM Controller Select Low Register[3]) does not function.
322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 301 Performance Counters Do Not Accurately Count MFENCE or SFENCE Instructions Description MFENCE and SFENCE instructions are not accurately counted by the performance monitor when MSRC001_000[3:0][7:0] (EventSelect) is 1D4h, or 1D5h. Potential Effect on System Performance monitoring software will not be able to count MFENCE and SFENCE instructions. Suggested Workaround None.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 302 MWAIT Power Savings May Not Be Realized when Two or More Cores Monitor the Same Address Description Execution of the MONITOR instruction may cause another core to exit the monitor event pending state. Potential Effect on System No functional impact; however, the power savings associated with the MWAIT instruction may not be realized. Suggested Workaround Contact your AMD representative for information on a BIOS update.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 308 Processor Stall in C1 Low Power State Description Under a highly specific set of internal timing conditions, an L3 eviction may stall for a processor core that has entered the C1 (Halt) state. If the processor core has already entered the low power state and the CpuPrbEn bit in the C1 SMAF is 0b (F3x84[24]), the stall persists until the processor core comes out of the low power state.
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 309 Processor Core May Execute Incorrect Instructions on Concurrent L2 and Northbridge Response Description Under a specific set of internal timing conditions, an instruction fetch may receive responses from the L2 and the Northbridge concurrently. When this occurs, the processor core may execute incorrect instructions. Potential Effect on System Unpredictable system behavior.
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Revision Guide for AMD Family 10h Processors 41322 Rev. 3.16 February 2008 315 FST and FSTP Instructions May Calculate Operand Address in Incorrect Mode Description A Floating-Point Store Stack Top (FST or FSTP) instruction in 64-bit mode that is followed shortly by an instruction that changes to compatibility mode may incorrectly calculate the operand address using compatibility mode.
41322 Rev. 3.16 February 2008 Revision Guide for AMD Family 10h Processors 319 Inaccurate Temperature Measurement Description The internal thermal sensor used for CurTmp (F3xA4[31:21]), hardware thermal control (HTC), software thermal control (STC), and the sideband temperature sensor interface (SB-TSI) may report inconsistent values. Potential Effect on System HTC, STC and SB-TSI do not provide reliable thermal protection. This does not affect THERMTRIP. Suggested Workaround None.
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