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AMD Geode™ SC3200 Processor Data Book

AMD Geode™ SC3200 Processor

Data Book

February 2007

Publication ID: 32581C

Summary of content (428 pages)

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AMD Geode™ SC3200 Processor Data Book February 2007 Publication ID: 32581C AMD Geode™ SC3200 Processor Data Book
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© 2007 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice.
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Contents 32581C Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 1.2 2.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . .
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32581C 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.1 6.2 6.3 6.4 7.0 Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 32581C List of Figures Figure 1-1. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. Figure 5-8. Figure 5-9. Figure 5-10. Figure 5-11. Figure 5-12. Figure 5-13. Figure 5-14. Figure 5-15. Figure 5-16. Figure 5-17. Figure 5-18. Figure 5-19. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. Figure 6-10. Figure 6-11. Figure 6-12. Figure 6-13.
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32581C Figure 7-6. Figure 7-7. Figure 7-8. Figure 7-9. Figure 7-10. Figure 7-11. Figure 7-12. Figure 7-13. Figure 7-14. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 9-7. Figure 9-8. Figure 9-9. Figure 9-10. Figure 9-11. Figure 9-12. Figure 9-13. Figure 9-14. Figure 9-15. Figure 9-16. Figure 9-17. Figure 9-18. Figure 9-19. Figure 9-20. Figure 9-21. Figure 9-22. Figure 9-23. Figure 9-24. Figure 9-25. Figure 9-26. Figure 9-27. Figure 9-28. Figure 9-29. Figure 9-30.
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32581C List of Figures Figure 9-47. Figure 9-48. Figure 9-49. Figure 9-50. Figure 9-51. Figure 9-52. Figure 9-53. Figure 9-54. Figure 9-55. Figure 9-56. Figure 9-57. Figure 9-58. Figure 10-1. Figure 10-2. Figure 10-3. AC97 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 AC97 Sync Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 AC97 Clocks Diagram . . . . . . . . .
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32581C 8 List of Figures AMD Geode™ SC3200 Processor Data Book
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List of Tables 32581C List of Tables Table 2-1. Table 2-2. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 5-11. Table 5-12. Table 5-13. Table 5-14. Table 5-15. Table 5-16. Table 5-17. Table 5-18. Table 5-19. Table 5-20. Table 5-21. Table 5-22. Table 5-23. Table 5-24.
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32581C Table 5-29. Table 5-30. Table 5-31. Table 5-32. Table 5-33. Table 5-34. Table 5-35. Table 5-36. Table 5-37. Table 5-38. Table 5-39. Table 5-40. Table 5-41. Table 5-42. Table 5-43. Table 5-44. Table 5-45. Table 5-46. Table 5-47. Table 5-48. Table 5-49. Table 5-50. Table 5-51. Table 5-52. Table 5-53. Table 5-54. Table 5-55. Table 5-56. Table 5-57. Table 5-58. Table 5-59. Table 5-60. Table 5-61. Table 5-62. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 6-8.
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32581C List of Tables Table 6-22. Table 6-23. Table 6-24. Table 6-25. Table 6-26. Table 6-27. Table 6-28. Table 6-29. Table 6-30. Table 6-31. Table 6-32. Table 6-33. Table 6-34. Table 6-35. Table 6-36. Table 6-37. Table 6-38. Table 6-39. Table 6-40. Table 6-41. Table 6-42. Table 6-43. Table 6-44. Table 6-45. Table 6-46. Table 6-47. Table 6-48. Table 6-49. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Table 7-8. Table 8-1. Table 9-1. Table 9-2. Table 9-3. Table 9-4.
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32581C Table 9-19. Table 9-20. Table 9-21. Table 9-22. Table 9-23. Table 9-24. Table 9-25. Table 9-26. Table 9-27. Table 9-28. Table 9-29. Table 9-30. Table 9-31. Table 9-33. Table 9-34. Table 9-35. Table 9-36. Table 9-37. Table 9-38. Table 9-39. Table 9-40. Table 9-41. Table 9-42. Table 9-43. Table 9-44. Table 9-45. Table 10-1. Table 10-2. Table A-1. 12 List of Tables PCI Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Overview 32581C 1 1.0Overview 1.1 General Description The AMD Geode™ SC3200 processor is a member of the AMD Geode family of fully integrated x86 system chips. The SC3200 processor includes: • The AMD Geode GX1 processor module combines advanced CPU performance with MMX™ support, fully accelerated 2D graphics, a 64-bit synchronous DRAM (SDRAM) interface, a PCI bus controller, and a display controller.
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32581C 1.2 Overview Features General Features Video Processor Module ■ 32-Bit x86 processor, up to 266 MHz, with MMX instruc- ■ Video Accelerator: tion set support ■ Memory controller with 64-bit SDRAM interface ■ 2D graphics accelerator ■ CCIR-656 video input port with direct video for full screen display ■ PC/AT functionality ■ PCI bus controller ■ IDE interface, two channels ■ USB, three ports, OHCI (OpenHost Controller Interface) version 1.0 compliant ■ Audio, AC97/AMC97 version 2.
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32581C Overview ■ PCI Bus Interface: — — — — — PCI v2.1 compliant with wakeup capability 32-Bit data path, up to 33 MHz Glueless interface for an external PCI device Fixed priority 3.
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32581C 16 Overview AMD Geode™ SC3200 Processor Data Book
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Architecture Overview 32581C 2 2.0Architecture Overview As illustrated in Figure 1-1 on page 13, the SC3200 processor contains the following modules in one integrated device: • GX1 Module: — Combines advanced CPU performance with MMX support, fully accelerated 2D graphics, a 64-bit synchronous DRAM (SDRAM) interface and a PCI bus controller. Integrates GX1 silicon revision 8.1.1.
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32581C Architecture Overview Table 2-1. SC3200 Memory Controller Register Summary GX_BASE+ Memory Offset Width (Bits) Type Name/Function Reset Value 8400h-8403h 32 R/W MC_MEM_CNTRL1. Memory Controller Control Register 1 248C0040h 8404h-8407h 32 R/W MC_MEM_CNTRL2. Memory Controller Control Register 2 00000801h 8408h-840Bh 32 R/W MC_BANK_CFG. Memory Controller Bank Configuration 41104110h 840Ch-840Fh 32 R/W MC_SYNC_TIM1.
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32581C Architecture Overview Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description 4 RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes. 3 XBUSARB (X-Bus Round Robin). When round robin is enabled, processor, graphics pipeline, and low priority display controller requests are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a higher priority level.
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32581C Architecture Overview Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description GX_BASE+8408h-840Bh 31:16 MC_BANK_CFG (R/W) Reset Value: 41104110h RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write as 0. 14 SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM for SODIMM: 0: 1 Module bank (Bank 0 only) 1: 2 Module banks (Bank 0 and 1) 13 RSVD (Reserved). Write as 0.
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32581C Architecture Overview Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description 11 RSVD (Reserved). Write as 0. 10:8 7 6:4 RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command to two different component banks within the same module bank. The memory controller does not perform back-to-back Activate commands to two different component banks without a READ or WRITE command between them. Hence, this field should be written as 001.
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32581C 2.1.2 Fast-PCI Bus The GX1 module communicates with the Core Logic module via a Fast-PCI bus that can work at up to 66 MHz. The Fast-PCI bus is internal for the SC3200 and is connected to the General Configuration Block (see Section 4.0 on page 69 for details on the General Configuration Block). This bus supports seven bus masters. The requests (REQs) are fixed in priority. The seven bus masters in order of priority are: 2.2.
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32581C Architecture Overview • Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals" on page 57, Section 6.2.5 "Sub-ISA Bus Interface" on page 145, and Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 70 • GPIO: See Section 3.4.16 "GPIO Interface Signals" on page 65. • More detailed information about each of these interfaces is provided in Section 6.2 "Module Architecture" on page 140. • Super/IO Block Interfaces: See Section 4.
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32581C 24 Architecture Overview AMD Geode™ SC3200 Processor Data Book
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Signal Definitions 32581C 3 3.0Signal Definitions This section defines the signals and describes the external interface of the SC3200. Figure 2-1 shows the signals organized by their functional groups. Where signals are multiplexed, the default signal name is listed first and is System Interface POR# X32I X32O X27I X27O PCIRST# BOOT16+ROMCS# LPC_ROM+PCICLK1 TFT_PRSNT+SDATA_OUT FPCI_MON+PCICLK0 DID0+GNT0#, DID1+GNT1# separated by a plus sign (+).
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32581C USB Interface Serial Ports (UARTs)/IDE Interface IR Port Interface AC97 Audio Interface Power Management Interface JTAG Interface Signal Definitions POWER_EN OVER_CUR# DPOS_PORT1 DNEG_PORT1 DPOS_PORT2 DNEG_PORT2 DPOS_PORT3 DNEG_PORT3 PCICLK0+FPCI_MON PCICLK1+LPC_ROM PCICLK INTA#, INTB# FRAME# AMD Geode™ LOCK# SC3200 PERR# Processor SERR# REQ[1:0]# GNT0#+DID0 SIN1 GNT1#+DID1 SIN2+SDTEST3 A[23:0]/AD[23:0] SOUT1+CLKSEL1 D[7:0]/AD[31:24] SOUT2+CLKSEL2 D[11:8]/C/BE[3:0]# GPIO7+RTS2#+IDE_DACK1#+SD
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32581C Signal Definitions 3.1 Ball Assignments The SC3200 is highly configurable as illustrated in Figure 3-1 on page 25. Strap options and register programming are used to set various modes of operation and specific signals on specific balls. This section describes which signals are available on which balls and provides configuration information: • Figure 3-2 on page 28: Illustrates the BGU481 ball assignments. Table 3-1.
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32581C A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL 1 2 VSS VIO 3 4 5 6 7 Signal Definitions 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 S AD30 PCK0 REQ1# PRST# PCICK IOW# GP20 GP17 HSNC VIO VSS NC NC VSS VPLL2 PD7 VSS NC VIO BUSY ACK# VSS PD6 PD1 STB# NC NC NC D+P3 D-P3 D+P1 D-P1 VIO VSS VIO SLIN# INIT# VSS NC VSS VSS VSS VIO PD5 VIO NC NC VIO INTB# AVSSUSB GP9 GP7 GP8 VSS INTA# AVCCUSB GP6 SOUT TDP TD
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32581C Signal Definitions Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number I/O Buffer1 Power Rail Configuration (PU/PD) Type Ball No. Signal Name A1 VSS GND --- --- --- A2 VIO PWR --- --- --- A3 AD30 I/O INPCI, OPCI VIO Cycle Multiplexed D6 I/O INPCI, OPCI A4 PCICLK0 O OPCI VIO INSTRP I (PD100) A5 REQ1# I (PU22.
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32581C Table 3-2. Ball No. Signal Name B6 AD23 Signal Definitions BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power Rail Configuration (PU/PD) Type I/O INPCI, OPCI VIO Cycle Multiplexed Ball No.
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32581C Signal Definitions Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power Rail Configuration (PU/PD) Type Ball No.
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581C Table 3-2. Signal Definitions BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power Rail Configuration (PU/PD) Type Ball No. Signal Name D10 GPIO1 I/O (PU22.5) INT, O3/5 VIO IOCS1# O (PU22.5) O3/5 TFTD12 O (PU22.5) TRDE# Ball No. Signal Name PMR[23]3 = 0 and PMR[13] = 0 D26 INTA# VIO PMR[23]3 = 0 and PMR[13] = 1 D27 AVCCUSB D28 O1/4 VIO PMR[23]3 = 1 O O3/5 VIO PMR[12] = 0 GPIO0 I/O (PU22.
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32581C Signal Definitions Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power (PU/PD) Type Rail Configuration Ball No. Signal Name F29 TDI I (PU22.5) INPCI VIO --- F30 GTEST I (PD22.5) INT VIO --- F31 VPCKIN I INT VIO --- G1 STOP# I/O (PU22.5) INPCI, OPCI VIO Cycle Multiplexed D15 I/O (PU22.
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32581C Table 3-2. Signal Definitions BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power Rail Configuration (PU/PD) Type Ball No. Signal Name L29 GPIO35 I/O (PU22.5) INPCI, OPCI LAD3 I/O (PU22.5) INPCI, OPCI GPIO34 I/O (PU22.5) INPCI, OPCI LAD2 I/O (PU22.5) INPCI, OPCI GPIO33 I/O (PU22.5) INPCI, OPCI LAD1 I/O (PU22.5) INPCI, OPCI L30 L31 VIO PMR[14]4 = 0 and PMR[22]4 = 0 Signal Name N29 GPIO12 I/O (PU22.5) INAB, O8/8 AB2C I/O (PU22.
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32581C Signal Definitions Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power Rail Configuration (PU/PD) Type Ball No. Signal Name R17 VSS GND --- --- --- R18 VSS GND --- --- --- R19 VSS GND --- --- --- R28 VSS GND --- --- --- R29 VSS GND --- --- --- Ball No.
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32581C Table 3-2. Ball No. Signal Name W285 MD57 W29 SDCLK1 W30 VSS Signal Definitions BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power (PU/PD) Type Rail Configuration Ball No.
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32581C Signal Definitions Table 3-2. Ball No.
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32581C Table 3-2. Signal Definitions BGU481 Ball Assignment - Sorted by Ball Number (Continued) I/O Buffer1 Power Rail Configuration (PU/PD) Type Ball No. I/O Buffer1 Power (PU/PD) Type Rail Configuration Ball No.
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32581C Signal Definitions Table 3-2. Ball No.
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32581C Signal Definitions Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name Signal Name Ball No. Signal Name U1 AD18 A1 P3 A2 U3 A3 A4 Ball No. Signal Name Ball No.
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32581C Signal Definitions Table 3-3. Signal Name F_STOP# F_TRDY# BGU481 Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Ball No. Signal Name Ball No. Signal Name U29 IDE_DATA1 AC1 LOCK# Ball No.
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32581C Table 3-3. Signal Definitions BGU481 Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Ball No. Signal Name Ball No.
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32581C Signal Definitions Table 3-3. Signal Name VIO (Total of 46) BGU481 Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Ball No.
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32581C 3.2 Signal Definitions Strap Options Several balls are read at power-up that set up the state of the SC3200. These balls are typically multiplexed with other functions that are outputs after the power-up sequence is complete. The SC3200 must read the state of the balls at power-up and the internal PU or PD resistors do not guarantee the correct state will be read. Therefore, it is required that an external PU or PD resistor with a value of 1.5 KΩ be placed on the balls listed in Table 3-4.
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32581C Signal Definitions 3.3 Multiplexing Configuration The tables that follow list multiplexing options and their configurations. Certain multiplexing options may be chosen per signal; others are available only for a group of signals. Where ever a GPIO pin is multiplexed with another function, there is an optional pull-up resistor on this pin; after system reset, the pull-up is present. This pull-up resistor can be disabled by writing Core Logic registers.
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32581C Signal Definitions Table 3-5. Two-Signal/Group Multiplexing (Continued) Default Ball No. Signal Alternate Configuration Signal Configuration GPIO N29 GPIO12 M29 GPIO13 ACCESS.
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32581C Signal Definitions Table 3-6. Three-Signal/Group Multiplexing (Continued) Default Ball No.
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32581C Signal Definitions Table 3-7. Four-Signal/Group Multiplexing Ball No.
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32581C Signal Definitions 3.4 Signal Descriptions Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identical information. 3.4.1 System Interface Signal Name Ball No. Type CLKSEL1 AF3 I CLKSEL0 B8 Description Fast-PCI Clock Selects. These strap signals are used to set the internal Fast-PCI clock. Mux SOUT1 RD# 00 = 33.3 MHz 01 = 48 MHz 10 = 66.7 MHz 11 = 33.
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32581C 3.4.1 Signal Definitions System Interface (Continued) Signal Name Ball No. Type X32I AJ2 I/O X32O AJ3 X27I AG3 X27O AH2 CLK27M AA4 O 27 MHz Output Clock. Output of crystal oscillator. PCIRST# A6 O PCI and System Reset. PCIRST# is the reset signal for the PCI bus and system. It is asserted for approximately 100 µs after POR# is negated. 3.4.2 I/O Description Mux Crystal Connections. Connected directly to a 32.768 KHz crystal.
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32581C Signal Definitions 3.4.2 Memory Interface Signals (Continued) Signal Name Ball No. Type DQM7 AB31 O DQM6 AG29 DQM5 AK21 DQM4 AL15 DQM3 AC31 Description Mux Data Mask Control Bits. During memory read cycles, these outputs control whether SDRAM output buffers are driven on the MD bus or not. All DQM signals are asserted during read cycles. --- During memory write cycles, these outputs control whether or not MD data is written into SDRAM.
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32581C 3.4.4 Signal Definitions TFT Interface Signals Signal Name Ball No. Type Description Mux HSYNC A11 O Horizontal Sync --- VSYNC B11 O Vertical Sync --- TFTDCK AA1 O TFT Clock. IDE_RST# A10 TFTDE P2 GPIO17+ IOCS0# O TFT Data Enable. IDE_CS1# B18 FP_VDD_ON AB1 ACK#+FPCICLK O V30 TFTD[17:0] 3.4.5 O Digital RGB Data to TFT. TFTD[5:0] - Connect to the BLUE TFT inputs. TFTD[11:6] - Connect to GREEN TFT inputs. TFTD[17:12] - Connect to RED TFT inputs. Ball No.
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32581C Signal Definitions 3.4.6 PCI Bus Interface Signals Signal Name BalL No. Type PCICLK A7 I PCI Clock. PCICLK provides timing for all transactions on the PCI bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge. --- PCICLK0 A4 O FPCI_MON (Strap) PCICLK1 D6 O PCI Clock Outputs. PCICLK0 and PCICLK1 provide clock drives for the system at 33 MHz. These clocks are asynchronous to PCI signals.
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32581C 3.4.6 Signal Definitions PCI Bus Interface Signals (Continued) Signal Name FRAME# BalL No. Type D8 I/O Description Mux Frame Cycle. Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate the beginning of a bus transaction. While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phase. --- This signal is internally connected to a pull-up resistor.
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32581C Signal Definitions 3.4.6 PCI Bus Interface Signals (Continued) Signal Name LOCK# BalL No. Type H3 I/O Description Lock Operation. LOCK# indicates an atomic operation that may require multiple transactions to complete. When LOCK# is asserted, non-exclusive transactions may proceed to an address that is not currently locked (at least 16 bytes must be locked). A grant to start a transaction on PCI does not guarantee control of LOCK#.
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32581C 3.4.6 Signal Definitions PCI Bus Interface Signals (Continued) Signal Name BalL No. Type REQ1# A5 I REQ0# B5 Description Mux Request Lines. REQ[1:0]# indicate to the arbiter that an agent requires the bus. Each master has its own REQ# line. REQ# priorities (in order) are: 1) VIP 2) IDE Channel 0 3) IDE Channel 1 4) Audio 5) USB 6) External REQ0# 7) External REQ1#. ----- Each REQ# is internally connected to a pull-up resistor. GNT1# C6 GNT0# C5 O Grant Lines.
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32581C Signal Definitions 3.4.7 Sub-ISA Interface Signals Signal Name Ball No. Type A[23:0] See Table 3-3 on page 40. O Address Lines D15 See Table 3-3 on page 40. I/O Data Bus D14 Description Mux AD[23:0] STOP# IRDY# D13 TRDY# D12 PAR D11 C/BE3# D10 C/BE2# D9 C/BE1# D8 C/BE0# D[7:0] BHE# IOCS1# AD[31:24] E4 O Byte High Enable. With A0, defines byte accessed for 16 bit wide bus cycles.
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32581C 3.4.8 Signal Definitions Low Pin Count (LPC) Bus Interface Signals Signal Name Ball No. Type LAD3 L29 I/O LAD2 L30 LAD1 L31 GPIO33 LAD0 M28 GPIO32 LDRQ# L28 I Description Mux LPC Address-Data. Multiplexed command, address, bidirectional data, and cycle status. LPC DMA Request. Encoded DMA request for LPC interface. Note: GPIO35 GPIO34 GPIO36 If LDRQ# function is selected but not used, tie LDRQ# high. LFRAME# K31 O LPC Frame.
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32581C Signal Definitions 3.4.9 IDE Interface Signals (Continued) Signal Name Ball No. Type IDE_IORDY0 AD1 I IDE_IORDY1 B29 I Description I/O Ready Channels 0 and 1. When de-asserted, these signals extend the transfer cycle of any host register access if the required device is not ready to respond to the data transfer request. Note: IDE_DREQ0 AC4 I IDE_DREQ1 C31 I IDE_DACK0# AD4 O IDE_DACK1# C30 O IRQ14 AF1 I IRQ15 AJ8 I 3.4.
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32581C 3.4.11 Signal Definitions Serial Ports (UARTs) Interface Signals Signal Name Ball No. Type SIN1 AG2 I SIN2 E28 SIN3 AK8 SOUT1 AF3 SOUT2 D29 SOUT3 C11 RTS2# C30 CTS2# C31 Description Serial Inputs. Receive composite serial data from the communications link (peripheral device, modem or other data transfer device). Note: O AG1 DTR2#/BOUT2 D28 If selected as SIN2 or SIN3 function(s) but not used, then signal(s) should be tied high. --SDTEST3 IRRX1 Serial Outputs.
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32581C Signal Definitions 3.4.12 Parallel Port Interface Signals Signal Name Ball No. Type Description Mux ACK# B18 I Acknowledge. Pulsed low by the printer to indicate that it has received data from the Parallel Port. TFTDE+FPCICLK AFD#/DSTRB# D22 O Automatic Feed. When low, instructs the printer to automatically feed a line after printing each line. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.
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32581C 3.4.12 Signal Definitions Parallel Port Interface Signals (Continued) Signal Name Ball No. Type STB#/WRITE# A22 O Description Mux Data Strobe. When low, indicates to the printer that valid data is available at the printer port. This signal is in TRISTATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be employed. TFTD17+ F_FRAME# Write Strobe. Active low, used in EPP mode to denote an address or data cycle.
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32581C Signal Definitions 3.4.14 AC97 Audio Interface Signals Signal Name BIT_CLK Ball No. Type U30 I Description Audio Bit Clock. The serial bit clock from the codec. Note: Mux F_TRDY# If selected as BIT_CLK function but not used, tie BIT_CLK low. SDATA_OUT P29 O Serial Data Output. This output transmits audio serial data to the codec. TFT_PRSNT (Strap) SDATA_IN U31 I Serial Data Input. This input receives serial data from the primary codec.
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32581C 3.4.15 Signal Definitions Power Management Interface Signals Signal Name Ball No. Type Description Mux CLK32 AH8 O 32.768 KHz Output Clock --- GPWIO0 AH6 I/O --- GPWIO1 AK5 General Purpose Wakeup I/Os. These signals each have an internal pull-up of 100 KΩ. GPWIO2 AJ6 LED# AL4 O LED Control. Drives an externally connected LED (on, off or a 1 Hz blink). Sleeping / Working indicator. This signal is an open-drain output. --- ONCTL# AJ5 O On / Off Control.
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32581C Signal Definitions 3.4.16 GPIO Interface Signals Signal Name Ball No. Type GPIO0 D11 I/O GPIO1 D10 N30 Description GPIO Port 0. Each signal is configured independently as an input or I/O, with or without static pull-up, and with either open-drain or totem-pole output type. A debouncer and an interrupt can be enabled or masked for each of signals GPIO[00:01] and [06:15] independently.
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32581C 3.4.17 Signal Definitions Debug Monitoring Interface Signals Signal Name Ball No.
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32581C Signal Definitions 3.4.18 JTAG Interface Signals (Continued) Signal Name TRST# Ball No. Type E29 I Description JTAG Test Reset. This signal has an internal weak pullup resistor. Mux --- For normal JTAG operation, this signal should be active at power-up. If the JTAG interface is not being used, this signal can be tied low. 3.4.19 Test and Measurement Interface Signals Signal Name Ball No. Type GXCLK V30 O GX Clock. This signal is for internal testing only.
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32581C 3.4.20 Signal Definitions Power, Ground and No Connections1 Signal Name Ball No. Type Description AVSSPLL2 C16 GND Analog PLL2 Ground Connection. AVSSPLL3 AK3 GND Analog PLL3 Ground Connection. VPLL2 A17 PWR 3.3V PLL2 Analog Power Connection. Low noise power for PLL2 and PLL5. VPLL3 AJ4 PWR 3.3V PLL3 Analog Power Connection. Low noise power for PLL3, PLL4, and PLL6. AVCCUSB D27 PWR 3.3V Analog USB Power Connection. Low noise power.
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General Configuration Block 32581C 4 4.0General Configuration Block The General Configuration block includes registers for: • Pin Multiplexing and Miscellaneous Configuration • WATCHDOG Timer • High-Resolution Timer • Clock Generators A selectable interrupt is shared by all these functions. not have a register block in PCI configuration space (i.e., they do not appear to software as PCI registers). After system reset, the Base Address register is located at I/O address 02EAh.
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32581C 4.2 General Configuration Block Multiplexing, Interrupt Selection, and Base Address Registers The registers described inTable 4-2 are used to determine general configuration for the SC3200. These registers also indicate which multiplexed signals are issued via balls from which more than one signal may be output. For more information about multiplexed signals and the appropriate configurations, see Section 3.1 "Ball Assignments" on page 27. Table 4-2.
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32581C General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 25 AC97CKEN (Enable AC97_CLK Output). This bit enables the output drive of AC97_CLK (ball P31). 0: AC97_CLK output is HiZ. 1: AC97_CLK output is enabled. 24 TFTIDE (TFT/IDE). Determines whether certain balls are used for TFT signals or for IDE signals. Note that there are no additional dependencies.
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32581C General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 23 TFTPP (TFT/Parallel Port). Determines whether certain balls are used for TFT or PP/ACB1/FPCI. This bit is set to 1 at power-on if the TFT_PRSNT strap (ball P29) is pulled high.
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32581C General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 21 IOCSEL (Select I/O Commands). Selects ball functions. Ball # 0: I/O Command Signals Name Add’l Dependencies 1: GPIO Signals Name Add’l Dependencies F1 / D9 IOR# DOCR# PMR[2] = 0 PMR[2] = 1 GPIO14 Undefined PMR[2] = 1 PMR[2] = 0 G3 / A8 IOW# DOCW# PMR[2] = 0 PMR[2] = 1 GPIO15 Undefined PMR[2] = 1 PMR[2] = 0 20 Reserved. Must be set to 0.
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32581C General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 12 TRDESEL (Select TRDE#). Selects ball function. 11 Ball # 0: Sub-ISA Signal Name Add’l Dependencies 1: GPIO Signal Name Add’l Dependencies H1 / D11 TRDE# GPIO0 None None EIDE (Enable IDE Outputs). This bit enables IDE output signals. 0: IDE signals are HiZ. Other signals multiplexed on the same balls are HiZ until this bit is set.
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General Configuration Block 32581C Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 16 Delay HSYNC. HSYNC delay by two TFT clock cycles. 0: There is no delay on HSYNC. 1: HYSNC is delayed twice by rising edge of TFT clock. Enables delay between VSYNC and HSYNC suited for TFT display. 15 Reserved. Write as read. 14 IBUS16 (Invert BUS16). This bit inverts the meaning of MCR[3] (bit 3 of this register). 0: BUS16 is as described for MCR[3].
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32581C General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit 0 Description SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’s PCI Control Function 2 Register (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI slave. SDBE[1:0] 00: Read and Write disconnect on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register (Index 41h).
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32581C General Configuration Block 4.3 WATCHDOG The SC3200 includes a WATCHDOG function to serve as a fail-safe mechanism in case the system becomes hung. When triggered, the WATCHDOG mechanism returns the system to a known state by generating an interrupt, an SMI, or a system reset (depending on configuration). 4.3.1 • The GX1 module’s internal SUSPA# signal is 1. or • The GX1 module’s internal SUSPA# signal is 0 and the WD32KPD bit (Offset 02h[8]) is 0.
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32581C General Configuration Block WATCHDOG Interrupt The WATCHDOG interrupt (if configured and enabled) is routed to an IRQ signal. The IRQ signal is programmable via the INTSEL register (Offset 38h, described in Table 4-2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 70). The WATCHDOG interrupt is a shareable, active low, level interrupt. WATCHDOG SMI The WATCHDOG SMI is recognized by the Core Logic module as internal input signal EXT_SMI0#.
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32581C General Configuration Block Table 4-3. WATCHDOG Registers (Continued) Bit Description Offset 04h WATCHDOG Status Register - WDSTS (R/WC) This register contains WATCHDOG status information. 7:4 Reset Value: 00h Reserved. Write as read. 3 WDRST (WATCHDOG Reset Asserted). (Read Only) This bit is set to 1 when WATCHDOG Reset is asserted. It is set to 0 when POR# is asserted, or when the WDOVF bit is set to 0. 2 WDSMI (WATCHDOG SMI Asserted).
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32581C General Configuration Block Table 4-4. High-Resolution Timer Registers Bit Description Offset 08h-0Bh TIMER Value Register - TMVALUE (RO) This register contains the current value of the High-Resolution Timer. 31:0 Reset Value: xxxxxxxxh Current Timer Value. Offset 0Ch TIMER Status Register - TMSTS (R/W) This register supplies the High-Resolution Timer status information. 7:1 0 Reset Value: 00h Reserved. TMSTS (TIMER Status).
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32581C General Configuration Block 4.5 Clock Generators and PLLs This section describes the registers for the clocks required by the GX1 module, Core Logic module, and the Video Processor, and how these clocks are generated. See Figure 4-2 for a clock generation diagram. The clock generators are based on 32.768 KHz and 27.000 MHz crystal oscillators. The 32.768 KHz crystal oscillator is described in Section 5.5.2 "RTC Clock Generation" on page 103 (functional description of the RTC).
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32581C 4.5.1 General Configuration Block 27 MHz Crystal Oscillator The internal oscillator employs an external crystal connected to the on-chip amplifier. The on-chip amplifier is accessible on the X27I input and X27O output signals. See Figure 4-3 for the recommended external circuit and Table 4-5 for a list of the circuit components. To other modules Internal External X27O X27I Choose C1 and C2 capacitors to match the crystal’s load capacitance.
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32581C General Configuration Block 4.5.2 GX1 Module Core Clock Table 4-6. Core Clock Frequency The core clock is generated by an Analog Delay Loop (ADL) clock generator from the internal Fast-PCI clock. The clock can be any whole-number multiple of the input clock between 4 and 10. Possible values are listed in Table 4-6. ADL Multiplier Value Internal Fast-PCI Clock Freq. (MHz) 33.33 48 66.
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32581C 4.5.4 SuperI/O Clocks The SuperI/O module requires a 48 MHz input for Fast infrared (FIR), UART, and other functions. This clock is supplied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz. 4.5.5 Core Logic Module Clocks The Core Logic module requires the following clock sources: Real-Time Clock (RTC) RTC requires a 32.768 KHz clock which is supplied directly from an internal low-power crystal oscillator.
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32581C General Configuration Block 4.5.7 Clock Registers Table 4-8 describes the registers of the clock generator and PLL. Table 4-8. Clock Generator Configuration Bit Description Offset 10h Maximum Core Clock Multiplier Register - MCCM (RO) Reset Value: Strapped Value This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock multiplied by this value. 7:4 Reserved. 3:0 MCM (Maximum Clock Multiplier).
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32581C General Configuration Block Table 4-8. Clock Generator Configuration (Continued) Bit Description Offset 1Eh-1Fh Core Clock Frequency Control Register - CCFC (R/W) This register controls the configuration of the core clock multiplier and the reference clocks. 15:14 Reserved. 13 Reserved. Must be set to 0. 12 Reserved. Must be set to 0. 11:10 9:8 Reset Value: Strapped Value Reserved. FPCICK (Internal Fast-PCI Clock).
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SuperI/O Module 32581C 5 5.0SuperI/O Module The SuperI/O (SIO) module is a PC98 and ACPI compliant SIO that offers a single-cell solution to the most commonly used ISA peripherals. The SIO module incorporates: two Serial Ports, an Infrared Communication Port that supports FIR, MIR, HP-SIR, Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284 Parallel Port, two ACCESS.bus Interface (ACB) ports, System Wakeup Control (SWC), and a Real-Time Clock (RTC) that provides RTC timekeeping.
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32581C 5.
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32581C SuperI/O Module Module Architecture The SIO module comprises a collection of generic functional blocks. Each functional block is described in detail later in this chapter. The beginning of this chapter describes the SIO structure and provides all device specific information, including special implementation of generic blocks, system interface and device configuration.
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32581C 5.3 SuperI/O Module Configuration Structure / Access This section describes the structure of the configuration register file, and the method of accessing the configuration registers. 5.3.1 Index-Data Register Pair The SIO configuration access is performed via an IndexData register pair, using only two system I/O byte locations. The base address of this register pair is determined according to the state of the IO_SIOCFG_IN bit field of the Core Logic module (F5BAR0+I/O Offset 00h[26:25]).
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32581C SuperI/O Module Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a nonexisting register or the LDN is 07h or higher than 08h), are ignored and a read returns 00h on all addresses except for 74h and 75h (DMA configuration registers) which returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset. 5.3.
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32581C 5.4 SuperI/O Module Standard Configuration Registers As illustrated in Figure 5-4, the Standard Configuration registers are broadly divided into two categories: SIO Control and Configuration registers and Logical Device Control and Configuration registers (one per logical device, some are optional). SIO Control and Configuration Registers The only PnP control register in the SIO module is the Logical Device Number register at Index 07h.
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32581C SuperI/O Module Table 5-3 provides the bit definitions for the Standard Configuration registers. • All reserved bits return 0 on reads, except where noted otherwise. They must not be modified as such modification may cause unpredictable results. Use read-modify- write to prevent the values of reserved bits from being changed during write. • Write only registers should not use read-modify-write during updates. Table 5-3.
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32581C SuperI/O Module Table 5-3. Standard Configuration Registers (Continued) Bit Description Index 75h DMA Channel Select 1 (R/W) Indicates selected DMA channel for DMA 1 of the logical device (1 - the second DMA channel in case of using more than one DMA channel). 7:3 2:0 Reserved. DMA 1 Channel Select: This bit field selects the DMA channel for DMA 1. The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active.
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32581C SuperI/O Module 5.4.1 SIO Control and Configuration Registers Table 5-4 lists the SIO Control and Configuration registers and Table 5-5 provides their bit formats. Table 5-4. SIO Control and Configuration Register Map Index Type 20h RO 21h Name Power Rail Reset Value SID. SIO ID VCORE F5h R/W SIOCF1. SIO Configuration 1 VCORE 01h 22h R/W SIOCF2. SIO Configuration 2 VPP 02h 27h RO SRID. SIO Revision ID VCORE 01h 2Eh --- RSVD. Reserved exclusively for AMD use.
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32581C 5.4.2 SuperI/O Module Logical Device Control and Configuration As described in Section 5.3.2 "Banked Logical Device Registers" on page 90, each functional block is associated with a Logical Device Number (LDN). This section provides the register descriptions for each LDN. 5.4.2.1 LDN 00h - Real-Time Clock Table 5-6 lists the registers which are relevant to configuration of the Real-Time Clock (RTC). Only the last registers (F0h-F3h) are described here (Table 5-7).
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32581C SuperI/O Module Table 5-7. RTC Configuration Registers Bit Description Index F0h RAM Lock Register - RLR (R/W) When any non-reserved bit in this register is set to 1, it can be cleared only by hardware reset. 7 Block Standard RAM. 0: No effect on Standard RAM access. (Default) 1: Read and write to locations 38h-3Fh of the Standard RAM are blocked, writes ignored, and reads return FFh. 6 Block RAM Write. 0: No effect on RAM access. (Default) 1: Writes to RAM (Standard and Extended) are ignored.
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32581C SuperI/O Module 5.4.2.2 LDN 01h - System Wakeup Control Table 5-8 lists registers that are relevant to the configuration of System Wakeup Control (SWC). These registers are described earlier in Table 5-3 "Standard Configuration Registers" on page 93. Table 5-8. Relevant SWC Registers 1. 98 Reset Value Index Type Configuration Register or Action 30h R/W Activate. When bit 0 is cleared, the registers of this logical device are not accessible.1 00h 60h R/W Base Address MSB register.
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32581C SuperI/O Module 5.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 3 Table 5-9 lists the configuration registers which affect the Infrared Communication Port or Serial Port 3 (IRCP/SP3). Only the last register (F0h) is described here (Table 5-10). See Table 5-3 "Standard Configuration Registers" on page 93 for descriptions of the other registers listed. Table 5-9. Relevant IRCP/SP3 Registers Reset Value Index Type Configuration Register or Action 30h R/W Activate.
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32581C SuperI/O Module 5.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2 Serial Ports 1 and 2 are identical, except for their reset values. Serial Port 1 is designated as LDN 03h and Serial Port 2 as LDN 08h. Table 5-11 lists the configuration registers which affect Serial Ports 1 and 2. Only the last register (F0h) is described here (Table 5-12). See Table 5-3 "Standard Configuration Registers" on page 93 for descriptions of the others. Table 5-11.
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32581C SuperI/O Module 5.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2 ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identical. Each ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. ACB1 and ACB2 use a 24 MHz internal clock. Six runtime registers for each ACCESS.bus are described in Section 5.7 "ACCESS.bus Interface" on page 119. ACB1 is designated as LDN 05h and ACB2 as LDN 06h. Table 5-13 lists the configuration registers which affect the ACCESS.bus ports.
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32581C SuperI/O Module 5.4.2.6 LDN 07h - Parallel Port The Parallel Port supports all IEEE 1284 standard communication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode). The Parallel Port includes two groups of runtime registers, as follows: • A group of 21 registers at first level offset, sharing 14 entries.
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32581C SuperI/O Module 5.5 Real-Time Clock (RTC) The RTC provides timekeeping and calendar management capabilities. The RTC uses a 32.768 KHz signal as the basic clock for timekeeping. It also includes 242 bytes of battery-backed RAM for general-purpose use. These locations may be reassigned, in compliance with Plug and Play requirements. The RTC provides the following functions: The RTC uses a 32.768 KHz clock signal as the basic clock for timekeeping. The 32.
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32581C External Elements Choose C1 and C2 capacitors (see Figure 5-5 on page 103) to match the crystal’s load capacitance. The load capacitance CL “seen” by crystal Y is comprised of C1 in series with C2 and in parallel with the parasitic capacitance of the circuit. The parasitic capacitance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 10 pF.
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32581C SuperI/O Module 5.5.2.4 Timekeeping Data Format Time is kept in BCD or binary format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24hour format, as determined by bit 1 of this register. Note: Method 2 1) Access the RTC registers after detection of an Update Ended interrupt. This implies that an update has just been completed and 999 ms remain until the next update. 2) When changing the above formats, re-initialize all the time registers. — Poll bit 4 of CRC.
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32581C SuperI/O Module 5.5.2.6 Power Supply The device is supplied from two supply voltages, as shown in Figure 5-8: • System standby power supply voltage, VSB • Backup voltage, from low capacity Lithium battery A standby voltage, VSB, from the external AC/DC power supply powers the RTC under normal conditions. Figure 5-9 represents a typical battery configuration. No external diode is required to meet the UL standard, due to the internal switch and internal serial resistor RUL.
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32581C SuperI/O Module 5.5.2.7 System Power States The system power state may be No Power, Power On, Power Off or Power Failure. Table 5-18 indicates the powersource combinations for each state. No other power-source combinations are valid. Power-Up Detection When system power is restored after a power failure or power off state (VSB = 0), the lockout condition continues for a delay of 62 ms (minimum) to 125 ms (maximum) after the RTC switches from battery to system power.
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32581C SuperI/O Module 5.5.2.9 Interrupt Handling The RTC has a single Interrupt Request line which handles the following three interrupt conditions: • Periodic interrupt. 5.5.2.10 Battery-Backed RAMs and Registers The RTC has two battery-backed RAMs and 17 registers, used by the logical units themselves. Battery-backup power enables information retention during system power down. The RAMs are: • Alarm interrupt. • Standard RAM • Update end interrupt.
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32581C SuperI/O Module 5.5.3 RTC Registers Note: The RTC registers can be accessed (see Section 5.4.2.1 "LDN 00h - Real-Time Clock" on page 96) at any time during normal operation mode (i.e.,when VSB is within the recommended operation range). This access is disabled during battery-backed operation. The write operation to these registers is also disabled if bit 7 of the CRD Register is 0. Before attempting to perform any start-up procedures, read about bit 7 (VRT) of the CRD Register.
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32581C SuperI/O Module Table 5-20. RTC Registers (Continued) Bit Description Index 03h 7:0 Minutes Alarm Register - MINA (R/W) Reset Type: VPP PUR Minutes Alarm Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format. When bits 7 and 6 are both set to 1, unconditional match is selected. See Section 5.5.2.5 "Alarms" on page 105 for more information about “unconditional” matches. Index 04h 7:0 Hours Data.
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32581C SuperI/O Module Table 5-20. RTC Registers (Continued) Bit Description 3 Reserved. This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is always read as 0. 2 Data Mode. This bit is reset at VPP power-up reset only. 0: Enable BCD format. 1: Enable Binary format. 1 Hour Mode. This bit is reset at VPP power-up reset only. 0: Enable 12-hour format. 1: Enable 24-hour format. 0 Daylight Saving. This bit is reset at VPP power-up reset only.
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32581C SuperI/O Module Table 5-21. Divider Chain Control / Test Selection DV2 DV1 DV0 CRA6 CRA5 CRA4 0 0 X Oscillator Disabled 0 1 0 Normal Operation 0 1 1 Test 1 0 X 1 1 X Table 5-22. Periodic Interrupt Rate Encoding Rate Select 3210 Periodic Interrupt Rate (ms) Divider Chain Output 0000 No interrupts 0001 3.906250 7 0010 7.812500 8 0011 0.122070 2 0100 0.244141 3 0101 0.488281 4 0110 0.976562 5 0111 1.953125 6 1000 3.906250 7 1001 7.
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32581C SuperI/O Module 5.5.3.1 Usage Hints 1) Read bit 7 of CRD at each system power-up to validate the contents of the RTC registers and the CMOS RAM. When this bit is 0, the contents of these registers and the CMOS RAM are questionable. This bit is reset when the backup battery voltage is too low. The voltage level at which this bit is reset is below the minimum recommended battery voltage, 2.4V. Although the RTC oscillator may function properly and the register contents may be correct at lower than 2.
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32581C 5.6 SuperI/O Module System Wakeup Control (SWC) The SWC wakes up the system by sending a power-up request to the ACPI controller in response to the following maskable system events: • Modem ring (RI2#) • Audio Codec event (SDATA_IN2) • Programmable Consumer Electronics IR (CEIR) address Each system event that is monitored by the SWC is fed into a dedicated detector that decides when the event is active, according to predetermined (either fixed or programmable) criteria.
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32581C SuperI/O Module 5.6.2 SWC Registers • Bank 0 holds reserved registers. The SWC registers are organized in two banks. The offsets are related to a base address that is determined by the SWC Base Address Register in the logical device configuration. The lower three registers are common to the two banks while the upper registers (03h-0Fh) are divided as follows: • Bank 1 holds the CEIR Control Registers.
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32581C SuperI/O Module Table 5-29. Banks 0 and 1 - Common Control and Status Registers Bit Description Offset 00h Wakeup Events Status Register - WKSR (R/W1C) Reset Value: 00h This register is set to 00h on power-up of VPP or software reset. It indicates which wakeup event and/or PME occurred. (See Section 6.2.9.4 "Power Management Events" on page 158.) 7 Reserved. 6 Reserved. Must be set to 0. 5 IRRX1 (CEIR) Event Status. This sticky bit shows the status of the CEIR event detection.
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32581C SuperI/O Module Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers Bit Description Bank 1, Offset 03h CEIR Wakeup Control Register - IRWCR (R/W) This register is set to 00h on power-up of VPP or software reset. 7:6 Reserved. 5:4 CEIR Protocol Select. Reset Value: 00h 00: RC5 01: NEC/RCA 1x: Reserved 3 Reserved. 2 Invert IRRX Input. 0: Not inverted. (Default) 1: Inverted. 1 Reserved. 0 CEIR Enable. 0: Disable. (Default) 1: Enable.
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32581C SuperI/O Module Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued) Bit Description CEIR Wakeup Range 1 Registers These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 5-26 on page 114). The values are represented in units of 0.1 ms. • RC-5 protocol: The pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. The nominal pulse width is 0.889 for a 38 KHz carrier.
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32581C SuperI/O Module 5.7 ACCESS.bus Interface The SC3200 has two ACCESS.bus (ACB) controllers. ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer, Intel's SMBus, and Philips’ I2C™. The ACB can be configured as a bus master or slave, and can maintain bidirectional communication with both multiple master and slave devices. As a slave device, the ACB may issue a request to become the bus master.
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32581C 5.7.3 SuperI/O Module Acknowledge (ACK) Cycle the ABD line (permits it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the ABD line during the ACK clock pulse, signalling that it has correctly received the last data byte and is ready to receive the next byte. Figure 5-16 illustrates the ACK cycle.
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32581C SuperI/O Module 5.7.4 Acknowledge After Every Byte Rule 5.7.6 According to this rule, the master generates an acknowledge clock pulse after each byte transfer, and the receiver sends an acknowledge signal after every byte received. There are two exceptions to this rule: • When the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave.
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32581C SuperI/O Module Sending the Address Byte When the device is the active master of the ACCESS.bus (ACBST[1] is set), it can send the address on the bus. Master Receive After becoming the bus master, the device can start receiving data on the ACCESS.bus. The address sent should not be the device’s own address, as defined by ACBADDR[6:0] if ACBADDR[7] is set, nor should it be the global call address if ACBST[3] is set.
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32581C SuperI/O Module Master Error Detection The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal condition is detected, ACBST[5] is set, and master mode is exited (ACBST[1] is cleared). 3) If ACBCTL1[2] is set, an interrupt is generated if both ACBCTL1[2] and ACBCTL16 are set.
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32581C 5.7.10 SuperI/O Module ACB Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 5.3.2 "Banked Logical Device Registers" on page 90). ACCESS.Bus Port 1 is assigned as LDN 05h and ACCESS.bus Port 2 as LDN 06h. In addition to the registers listed here, there are additional configuration registers listed in Section 5.4.2.5 "LDN 05h and 06h - ACCESS.bus Ports 1 and 2" on page 101. Table 5-31. ACB Register Map Reset Value Offset Type Name 00h R/W ACBSDA.
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32581C SuperI/O Module Table 5-32. ACB Registers (Continued) Bit 2 Description NMATCH (New Match). (R/W1C) Writing 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent when this bit is set. 0: Software writes 1 to this bit. 1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match. 1 MASTER. (RO) 0: Arbitration loss (BER, bit 5, is set) or recognition of a Stop Condition. 1: Bus master request succeeded and master mode active.
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32581C SuperI/O Module Table 5-32. ACB Registers (Continued) Bit 4 Description ACK (Acknowledge). This bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle. 0: Cleared after acknowledge cycle. 1: Negative acknowledge issued on next received byte. 3 Reserved. 2 INTEN (Interrupt Enable). 0: ACB interrupt disabled. 1: ACB interrupt enabled.
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32581C SuperI/O Module 5.8 Legacy Functional Blocks This section briefly describes the following blocks that provide legacy device functions: • Parallel Port. (Similar to Parallel Port in the National Semiconductor PC87338.) • Serial Port 1 and Serial Port 2 (SP1 and SP2), UART functionality for both SP1 and SP2. (Similar to SCC1 in the National Semiconductor PC87338.) • Infrared Communications Port / Serial Port 3 functionality. (Similar to SCC2 in the National Semiconductor PC87338.
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32581C SuperI/O Module Table 5-35.
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32581C SuperI/O Module 5.8.2 UART Functionality (SP1 and SP2) Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote peripheral device or modem using a wired interface. The functional blocks can function as a standard 16450, 16550, or as an Extended UART. Bank 3 Bank 2 Bank 1 Bank 0 5.8.2.1 UART Mode Register Bank Overview Four register banks, each containing eight registers, control UART operation.
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32581C SuperI/O Module Table 5-38. Bank Selection Encoding BSR Bits 7 6 5 4 3 2 1 0 Bank Selected 0 x x x x x x x 0 1 0 x x x x x x 1 1 1 x x x x 1 x 1 1 1 x x x x x 1 1 1 1 1 0 0 0 0 0 2 1 1 1 0 0 1 0 0 3 Table 5-39. Bank 1 Register Map Offset Type Name 00h R/W LBGD(L). Legacy Baud Generator Divisor Port (Low Byte) 01h R/W LBGD(H). Legacy Baud Generator Divisor Port (High Byte) 02h --- RSVD. Reserved 03h W LCR1.
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32581C SuperI/O Module Table 5-42.
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32581C SuperI/O Module Table 5-44. Bank 2 Bit Map Register Offset Name Bits 7 6 5 4 3 2 1 00h BGD(L) BGD[7:0] (Low Byte) 01h BGD(H) BGD [15:8] (High Byte) 02h EXCR1 BTEST 03h BSR BKSE 04h EXCR2 LOCK 05h RSVD 06h RXFLV RSVD RFL[4:0] 07h TXFLV RSVD TFL[4:0] RSVD ETDLBK LOOP 0 RSVD EXT_SL BSR[6:0] (Bank Select) RSVD PRESL[1:0] RSVD Reserved Table 5-45.
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32581C SuperI/O Module 5.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality Bank 7 This section describes the IRCP/SP3 support registers. The IRCP/SP3 functional block provides advanced, versatile serial communications features with IR capabilities. Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 The IRCP/SP3 also supports two DMA channels; the functional block can use either one or both of them.
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32581C SuperI/O Module Table 5-47. Bank Selection Encoding BSR Bits 7 6 5 4 3 2 1 0 Bank Selected Functionality 0 x x x x x x x 0 UART + IR 1 0 x x x x x x 1 1 1 x x x x 1 x 1 1 1 x x x x x 1 1 1 1 1 0 0 0 0 0 2 1 1 1 0 0 1 0 0 3 1 1 1 0 1 0 0 0 4 1 1 1 0 1 1 0 0 5 1 1 1 1 0 0 0 0 6 1 1 1 1 0 1 0 0 7 IR Only Table 5-48. Bank 1 Register Map Offset Type Name 00h R/W LBGD(L).
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32581C SuperI/O Module Table 5-50. Bank 3 Register Map Offset Type Name 00h RO MID. Module and Revision Identification 01h RO SH_LCR. Link Control Shadow 02h RO SH_FCR. FIFO Control Shadow 03h R/W BSR. Bank Select 04h-07h --- RSVD. Reserved Table 5-51. Bank 4 Register Map Offset Type 00h RO TMR(L). TImer (Low Byte) 01h RO TMR(H). Timer (High Byte) 02h R/W IRCR1. IR Control 1 03h R/W BSR. Bank Select 04h R/W TFRL(L). Transmission Frame Length (Low Byte) RO TFRCC(L).
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32581C SuperI/O Module Table 5-53. Bank 6 Register Map Offset Type Name 00h R/W IRCR3. IR Control 3 01h R/W MIR_PW. MIR Pulse Width 02h R/W SIR_PW. SIR Pulse Width 03h R/W BSR. Bank Select 04h R/W BFPL. Beginning Flags/Preamble Length 05h-07h --- RSVD. Reserved Table 5-54. Bank 7 Register Map Offset Type Name 00h R/W IRRXDC. IR Receiver Demodulator Control 01h R/W IRTXMC. IR Transmitter Modulator Control 02h R/W RCCFG. Consumer IR (CEIR) Configuration 03h R/W BSR.
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32581C SuperI/O Module Table 5-56. Bank 1 Bit Map Register Offset Bits Name 7 6 5 4 3 2 00h LBGD(L) LBGD[7:0] (Low Byte Data) 01h LBGD(H) LBGD[15:8] (High Byte Data) 02h RSVD 03h LCR BKSE BSR BKSE 04h-07h 1 0 RSVD SBRK STKP EPS PEN STB WLS[1:0] BSR[6:0] (Bank Select) RSVD RSVD Table 5-57.
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32581C SuperI/O Module Table 5-59. Bank 4 Bit Map (Continued) Register Offset Name 06h RFRML(L)/ RFRCC(L) 07h RFRML(H)/ RFRCC(H) Bits 7 6 5 4 3 2 1 0 RFRML[7:0] / RFRCC[7:0] (Low Byte Data) RSVD RFRML[12:8] / RFRCC[12:8] (High Byte Data) Table 5-60.
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Core Logic Module 32581C 6 6.0Core Logic Module The Core Logic module is an enhanced PCI-to-Sub-ISA bridge (South Bridge), this module is ACPI-compliant, and provides AT/Sub-ISA functionality. The Core Logic module also contains state-of-the-art power management. Two bus mastering IDE controllers are included for support of up to four ATA-compliant devices. A three-port Universal Serial Bus (USB) provides high speed, and Plug & Play expansion for a variety of new consumer peripheral devices. 6.
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32581C Core Logic Module Integrated Audio 6.2 • AC97 Version 2.0 compliant interface to audio codecs The Core Logic architecture provides the internal functional blocks shown in Figure 6-1.
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32581C Core Logic Module 6.2.1 Fast-PCI Interface to External PCI Bus The Core Logic module provides a PCI bus interface that is both a slave for PCI cycles initiated by the GX1 module or other PCI master devices, and a non-preemptive master for DMA transfer cycles. It is also a standard PCI master for the IDE controllers and audio I/O logic. The Core Logic supports positive decode for configurable memory and I/O regions, and implements a subtractive decode option for unclaimed PCI accesses.
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32581C 6.2.2.1 Video Retrace Interrupt Bit 7 of the “Serial Packet” can be used to generate an SMI whenever a video retrace occurs within the GX1 module. This function is normally not used for power management but for SoftVGA routines. Setting F0 Index 83h[2] = 1 enables this function. A read only status register located at F1BAR0+I/O Offset 00h[5] can be read to see if the SMI was caused by a video retrace event. 6.2.
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32581C Core Logic Module For example, if a channel had one Mode 4 device and one Mode 0 device, then the Mode 4 device would have command timings for Mode 0 and data timing for Mode 4. The Mode 0 device would have both command and data timings for Mode 0. Note that for the Mode 0 case, the 32-bit timing value is listed because both data and command timings are the same mode.
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32581C Core Logic Module 6.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic module supports UltraDMA/33. It utilizes the standard IDE Bus Master functionality to interface, initiate and control the transfer. UltraDMA/33 definition also incorporates a Cyclic Redundancy Checking (CRC) error checking protocol to detect errors. The UltraDMA/33 protocol requires no extra signal pins on the IDE connector. The IDE controller redefines three standard IDE control signals when in UltraDMA/33 mode.
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Core Logic Module 6.2.4 Universal Serial Bus The Core Logic module provides three complete, independent USB ports. Each port has a Data "Negative" and a Data "Positive" signal. The USB ports are Open Host Controller Interface (OpenHCI) compliant. The OpenHCI specification provides a register-level description for a host controller, as well as common industry hardware/software interface and drivers. 6.2.
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32581C Core Logic Module 6.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write results in two 16-bit ISA transactions or four 8bit ISA transactions. The ISA controller gathers the data from multiple ISA read cycles and returns TRDY# to the PCI bus. SA[23:0] are a concatenation of ISA LA[23:17] and SA[19:0] and perform equivalent functionality at a reduced pin count.
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32581C Core Logic Module REQ# GNT# FRAME# Fast-PCI 1 2 1 IRDY# 1 TRDY# STOP# 1 BALE ISA RD#, IOR# 3 1 - GX1 transaction 2 - IDE bus master - starts and completes 3 - End of ISA cycle Figure 6-3. PCI to ISA Cycles with Delayed Transaction Enabled 6.2.5.3 Sub-ISA Bus Data Steering The Core Logic module performs all of the required data steering from SD[7:0] to SD[15:0] during normal 8-bit ISA cycles, as well as during DMA and ISA master cycles.
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32581C Core Logic Module 6.2.5.5 ISA DMA DMA transfers occur between ISA I/O peripherals and system memory (i.e., not available externally). The data width can be either 8 or 16 bits. Out of the seven DMA channels available, four are used for 8-bit transfers while the remaining three are used for 16-bit transfers. One byte or WORD is transferred in each DMA cycle. Note: The Core Logic module does not support DMA transfers to ISA memory.
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32581C Core Logic Module 6.2.5.6 ROM Interface The Core Logic module positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) and FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory cycles cause the Core Logic module to claim the cycle, and generate an ISA bus memory cycle with ROMCS# asserted. The Core Logic module can also be configured to respond to memory addresses FF000000h-FFFFFFFFh (16 MB) and 000E0000h-000FFFFFh (128 KB). Table 6-3.
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32581C Core Logic Module PCI TCS Sub-ISA TCP PCI pull-up FRAME# TRDY#, IRDY# GNT[x] ROMCS#, DOCCS#, IOCS0#, IOCS1# PAR, DEVSEL#,STOP# AD[31:0], C/BE[3:0]# Figure 6-6. PCI Change to Sub-ISA and Back 6.2.
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Core Logic Module DMA Transfer Modes Each DMA channel can be programmed for single, block, demand or cascade transfer modes. In the most commonly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is released after every cycle. This allows the Core Logic module to timeshare the PCI bus with the GX1 module. This is imperative, especially in cases involving large data transfers, because the GX1 module gets locked out for too long.
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32581C DMA Addressing Capability DMA transfers occur over the entire 32-bit address range of the PCI bus. This is accomplished by using the DMA controller’s 16-bit memory address registers in conjunction with an 8-bit DMA Low Page register and an 8-bit DMA High Page register. These registers, associated with each channel, provide the 32-bit memory address capability. A write to the Low Page register clears the High Page register, for backward compatibility with the PC/AT standard.
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32581C Core Logic Module 6.2.6.3 Programmable Interrupt Controller The Core Logic module contains two 8259A-equivalent programmable interrupt controllers, with eight interrupt request lines each, for a total of 16 interrupts. The PCI device supports all x86 modes of operation except Special Fully Nested mode. The two controllers are cascaded internally, and two of the interrupt request inputs are connected to the internal circuitry. This allows a total of 13 externally available interrupt requests.
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32581C PIC Interrupt Sequence A typical AT-compatible interrupt sequence is as follows. Any unmasked interrupt generates the internal INTR signal to the CPU. The interrupt controller then responds to the interrupt acknowledge (INTA) cycles from the CPU. On the first INTA cycle the cascading priority is resolved to determine which of the two 8259A controllers output the interrupt vector onto the data bus.
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32581C Core Logic Module 6.2.7.1 I/O Port 092h System Control I/O Port 092h allows for a fast keyboard assertion of an A20# SMI and a fast keyboard CPU reset. Decoding for this register may be disabled via F0 Index 52h[3]. The assertion of a fast keyboard A20# SMI is controlled by either I/O Port 092h or by monitoring for the keyboard command sequence (see Section 6.2.8.1 "Fast Keyboard Gate Address 20 and CPU Reset" on page 155).
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32581C 6.2.
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32581C Core Logic Module 6.2.9.2 Sleep States The SC3200 supports four Sleep states (SL1-SL3) and the Soft Off state (G2/S5). These states are fully compliant with the ACPI specification, revision 1.0. When the SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]) is set to 1, the SC3200 enters an SLx state according to the SLP_TYPx field (F1BAR1+I/O Offset 0Ch[12:10]). It exits the Sleep state back to the S0 state (C0 state - Full Speed or Throttling, depending on the THT_EN bit) upon an enabled power management event.
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32581C Core Logic Module 6.2.9.3 Power Planes Control The SC3200 supports up to three power planes. Three signals are used to control these power planes. Table 6-6 describes the signals and when each is asserted. Table 6-6. Power Planes Control Signals vs. Sleep States S0 SL1 SL2 SL3 SL4 and SL5 PWRCNT1 1 1 0 0 0 PWRCNT2 1 1 1 0 0 ONCTL# 0 0 0 0 1 Signal These signals allow control of the power of system devices and the SC3200 itself.
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32581C Core Logic Module Power Button The power button (PWRBTN#) input provides two events: a wake request, and a sleep request. For both these events, the PWRBTN# signal is debounced (i.e., the signal state is transferred only after 14 to 16 ms without transitions, to ensure that the signal is no longer bouncing). ACPI is non-functional and all ACPI outputs are undefined when the power-up sequence does not include using the power button. SUSP# is an internal signal generated from the ACPI block.
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32581C 6.2.10 Power Management Programming The power management resources provided by a combined GX1 module and Core Logic module based system supports a high efficiency power management implementation. The following explanations pertain to a full-featured “notebook” power management system. The extent to which these resources are employed depends on the application and on the discretion of the system designer. Power management resources can be grouped according to the function they enable or support.
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32581C Core Logic Module The automatic speedup events (video and IRQ) for Suspend Modulation should be used together with softwarecontrolled speedup registers for major I/O events such as any access to the FDC, HDD, or parallel/serial ports, since these are indications of major system activities. When major I/O events occur, Suspend Modulation should be temporarily disabled using the procedures described in the Power Management registers in the following subsections.
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32581C 6.2.10.3 Peripheral Power Management The Core Logic module provides peripheral power management using a combination of device idle timers, address traps, and general purpose I/O pins. Idle timers are used in conjunction with traps to support powering down peripheral devices.
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32581C Core Logic Module Power Management SMI Status Reporting Registers The Core Logic module updates status registers to reflect the SMI sources. Power management SMI sources are the device idle timers, address traps, and general purpose I/O pins. Power management events are reported to the GX1 module through the active low SMI# signal. When an SMI is initiated, the SMI# signal is asserted low and is held low until all SMI sources are cleared. At that time, SMI# is deasserted.
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32581C Core Logic Module 6.2.10.4 Power Management Programming Summary Table 6-9 provides a programming register summary for the power management timers, traps, and functions. For com- plete bit information regarding the registers listed in Table 6-9, refer to Section 6.4.1 "Bridge, GPIO, and LPC Registers - Function 0" on page 188. Table 6-9.
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32581C Core Logic Module 6.2.11 GPIO Interface Up to 64 GPIOs in the in the Core Logic module are provided for system control. For further information, see Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 70 and Table 6-30 "F0BAR0+I/ O Offset: GPIO Configuration Registers" on page 222. Note: Not all GPIOs are available on SC3200 balls. GPIOs [63:42], [31:21], and [5:2] are reserved. 6.2.
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32581C Core Logic Module Physical Region Descriptor Table Address Before the bus master starts a master transfer it must be programmed with a pointer (PRD Table Address register) to a Physical Region Descriptor Table. This pointer sets the starting memory location of the Physical Region Descriptors (PRDs). The PRDs describe the areas of memory that are used in the data transfer. The descriptor table entries must be aligned on a 32-byte boundary and the table cannot cross a 64 KB boundary in memory.
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32581C Core Logic Module 4) Read the SMI Status register to clear the Bus Master Error and End of Page bits (bits 1 and 0). Set the correct direction to the Read or Write Control bit (Command register bit 3). Note that the direction of the data transfer of a particular bus master is fixed and therefore the direction bit must be programmed accordingly. It is assumed that the codec has been properly programmed to receive the audio data.
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32581C Core Logic Module 6.2.12.2 AC97 Codec Interface The AC97 codec (e.g., LM4548) is the master of the serial interface and generates the clocks to Core Logic module. Figure 6-13 shows the signal connections between two codecs and the SC3200: • Codec1 can be AC97 Rev. 1.3 or higher compliant. • Codec2 is optional, but must be compliant with AC97 2.0 or higher. (For specifics on the serial interface, refer to the appropriate codec manufacturer’s data book.) — SDATA_IN2 has wakeup capability.
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Core Logic Module 32581C 6.2.12.3 VSA Technology Support Hardware The Core Logic module incorporates the required hardware in order to support the Virtual System Architecture (VSA) technology for capture and playback of audio using an external codec. This eliminates much of the hardware traditionally associated with industry standard audio functions.
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32581C Core Logic Module In Fast Path Write, the Core Logic module responds to writes to the following addresses: 388h, 38Ah, 38Bh, 2x0h, 2x2h, and 2x8h. SMI# Asserted Table 6-38 on page 262 shows the bit formats of the second level SMI status reporting registers and the Fast Path Read/Write programming bits.
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32581C Core Logic Module 6.2.12.4 IRQ Configuration Registers The Core Logic module provides the ability to set and clear IRQs internally through software control. If the IRQs are configured for software control, they do not respond to external hardware.
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32581C 6.2.12.6 LPC Interface Signal Definitions The LPC specification lists seven required and six optional signals for supporting the LPC interface. Many of the signals are the same signals found on the PCI interface and do not require any new pins on the host. Required signals must be implemented by both hosts and peripherals. Optional signals may or may not be present on particular hosts or peripherals.
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32581C Core Logic Module - PCI Configuration Space and Access Methods 6.3 Register Descriptions The Core Logic module is a multi-function module. Its register space can be broadly divided into three categories in which specific types of registers are located: 1) Chipset Register Space (F0-F5) (Note that F4 is for Video Processor support, see Section 7.3.
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32581C 6.3.2 Core Logic Module - Register Summary Register Summary Note: The tables in this subsection summarize the registers of the Core Logic module. Included in the tables are the register’s reset values and page references where the bit formats are found. Function 4 (F4) is for Video Processor support (although accessed through the Core Logic PCI configuration registers). Refer to Section 7.3.1 "Register Summary" on page 327 for details. Table 6-14.
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Core Logic Module - Register Summary 32581C Table 6-14.
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32581C Core Logic Module - Register Summary Table 6-14.
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Core Logic Module - Register Summary 32581C Table 6-15.
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32581C Core Logic Module - Register Summary Table 6-17.
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Core Logic Module - Register Summary 32581C Table 6-19.
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32581C Core Logic Module - Register Summary Table 6-20.
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32581C Core Logic Module - Register Summary Table 6-21.
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32581C Core Logic Module - Register Summary Table 6-23.
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Core Logic Module - Register Summary 32581C Table 6-24.
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32581C Core Logic Module - Register Summary Table 6-26.
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Core Logic Module - Register Summary 32581C Table 6-27.
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32581C Core Logic Module - Register Summary Table 6-28.
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Core Logic Module - Register Summary 32581C Table 6-28.
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32581C 6.4 Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Chipset Register Space The Chipset Register Space of the Core Logic module is comprised of six separate functions (F0-F5), each with its own register space. Base Address Registers (BARs) in each PCI header register space set the base address for the configuration registers for each respective function. The configuration registers accessed through BARs are I/O or memory mapped.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 4 Description Memory Write and Invalidate. Allow the Core Logic module to do memory write and invalidate cycles, if the PCI Cache Line register (F0 Index 0Ch) is set to 32 bytes (08h). 0: Disable. (Default) 1: Enable. 3 Special Cycles. Allow the Core Logic module to respond to special cycles. 0: Disable. 1: Enable.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 08h Device Revision ID Register (RO) Index 09h-0Bh Index 0Ch 7:0 Reset Value: 00h PCI Class Code Register (RO) Reset Value: 060100h PCI Cache Line Size Register (R/W) Reset Value: 00h PCI Cache Line Size Register. This register sets the size of the PCI cache line, in increments of four bytes.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 40h PCI Function Control Register 1 (R/W) 7:6 Reserved. Must be set to 0. 5 Reserved. Must be set to 0. 4 PCI Subtractive Decode. Reset Value: 39h 0: Disable transfer of subtractive decode address to external PCI bus. External PCI bus is not usable.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 1 Description Power Management Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 1 (F1) register space, an SMI is generated. Writes are trapped; access to the register is denied. Reads are snooped; access to the register is allowed. 0: Disable. 1: Enable.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 2 Description IDE Reset. Reset IDE bus. 0: Disable. 1: Enable (drive IDE_RST# low). Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled. Note: 1 When X-Bus Warm Start is enabled (bit 0 = 1) or during POR#, IDE_RST# is put into TRI-STATE mode.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 4Ch-4Fh 31:0 Top of System Memory (R/W) Reset Value: FFFFFFFFh Top of System Memory. Highest address in system used to determine active decode for external PCI mastered memory cycles.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 52h 7 ROM/AT Logic Control Register (R/W) Reset Value: 98h Snoop Fast Keyboard Gate A20 and Fast Reset. Enables the snoop logic associated with keyboard commands for A20 Mask and Reset. 0: Disable snooping. The keyboard controller handles the commands. 1: Enable snooping. 6:5 4 Reserved. Must be set to 0.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 54h-59h Index 5Ah Reserved Reset Value: 00h Decode Control Register 1 (R/W) Reset Value: 01h Indicates PCI positive or negative decoding for various I/O ports on the ISA bus. Note: Positive decoding by the Core Logic module speeds up I/O cycle time.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 4 Secondary IDE Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 170h177h and 376h-377h (excluding writes to 377h). 0: Subtractive. Subtractively decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are then forwarded to ISA. 1: Positive.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 60h-63h 31:8 7 ACPI Control Register (R/W) Reset Value: 00000000h Reserved. Must be set to 0. SUSP_3V Shut Down PLL5. Allow internal SUSP_3V to shut down PLL5. 0: Clock generator is stopped when internal SUSP_3V is active. 1: 6 Clock generator continues working when internal SUSP_3V is active.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 70h-71h 15:0 IOCS1# Base Address Register (R/W) Reset Value: 0000h I/O Chip Select 1 Base Address. This 16-bit value represents the I/O base address used to enable assertion of IOCS1# (ball D10 or N30 - see PMR[23] in Table 4-2 on page 70).
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 78h-7Bh 31:0 DOCCS# Base Address Register (R/W) Reset Value: 00000000h DiskOnChip Chip Select Base Address. This 32-bit value represents the memory base address used to enable assertion of DOCCS# (BGU481 ball A9 or N31, see PMR[23] in Table 4-2 on page 70).
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 1 Description Idle Timers. Device idle timers. 0: Disable. 1: Enable. Note: 0 Disable at this level does not reload the timers on the enable. The timers are disabled at their current counts. This bit has no affect on the Suspend Modulation register (F0 Index 94h).
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 3 Description Keyboard/Mouse Idle Timer Enable. Turn on Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an SMI when the timer expires. 0: Disable. 1: Enable. If an access occurs in the address ranges listed below, the timer is reloaded with the programmed count: — Keyboard Controller: I/O Ports 060h/064h.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 82h 7 Power Management Enable Register 3 (R/W) Reset Value: 00h Video Access Trap. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GX1 module’s PSERIAL register), an SMI is generated. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 1 Description Floppy Disk Access Trap. 0: Disable. 1: Enable. If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated. — Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h. — Secondary floppy disk: I/O Port 372h-375h, 377h. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 2 Description Video Retrace Interrupt SMI. Allow SMI generation whenever video retrace occurs. 0: Disable. 1: Enable. This information is decoded from the serial connection (PSERIAL register, bit 7) from the GX1 module. This function is normally not used for power management but for soft (VSA) VGA routines.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 85h Second Level PME/SMI Status Mirror Register 2 (RO) Reset Value: 00h The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0]. This register is called a “Mirror” register since an identical register exists at F0 Index F5h.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 86h Second Level PME/SMI Status Mirror Register 3 (RO) Reset Value: 00h The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0]. This register is called a “Mirror” register since an identical register exists at F0 Index F6h.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 87h Second Level PME/SMI Status Mirror Register 4 (RO) Reset Value: 00h The bits in this register contain second level status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[0]. This register is called a “Mirror” register since an identical register exists at F0 Index F7h.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 89h 7 General Purpose Timer 1 Control Register (R/W) Reset Value: 00h General Purpose Timer 1 TImebase. Selects timebase for General Purpose Timer 1 (F0 Index 88h). 0: 1 second. 1: 1 millisecond. 6 Re-trigger General Purpose Timer 1 on User Defined Device 3 (UDEF3) Activity. 0: Disable. 1: Enable.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 8Ah 7:0 General Purpose Timer 2 Count Register (R/W) Reset Value: 00h GPT2_COUNT. This field represents the load value for General Purpose Timer 2. This value can represent either an 8-bit or 16-bit counter (configured in F0 Index 8Bh[5]).
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 8Eh 7:0 VGA Timer Count Register (R/W) Note: Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. It is not affected by the Global Power Management Enable setting at F0 Index 80h[0]. Index 8Fh-92h Index 93h 7 Reset Value: 00h VGA Timer Load Value.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 96h 7:3 2 Suspend Configuration Register (R/W) Reset Value: 00h Reserved. Must be set to 0. Suspend Mode Configuration. Special 3V Suspend mode to support powering down the GX1 module during Suspend. 0: Disable. 1: Enable. 1 SMI Speedup Configuration.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index 9Eh-9Fh 15:0 Keyboard / Mouse Idle Timer Count Register (R/W) Reset Value: 0000h Keyboard / Mouse Idle Timer Count. This idle timer determines when the keyboard and mouse are not in use so that the LCD screen can be blanked.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index ACh-ADh 15:0 Secondary Hard Disk Idle Timer Count Register (R/W) Reset Value: 0000h Secondary Hard Disk Idle Timer Count. This idle timer is used to determine when the secondary hard disk is not in use so that it can be powered down.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index B8h 7:0 DMA Shadow Register (RO) Reset Value: xxh DMA Shadow. This 8-bit port sequences through the following list of shadowed DMA Controller registers. At power on, a pointer starts at the first register in the list and continuing through the other registers in subsequent reads according to the read sequence.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index BBh 7:0 RTC Index Shadow Register (RO) Index BCh 7:4 Clock Stop Control Register (R/W) 0 Reset Value: 00h PLL Delay. The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the internal SUSP# signal is de-asserted to the GX1 module.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index CCh 7 User Defined Device 1 Control Register (R/W) Reset Value: 00h Memory or I/O Mapped. Determines how User Defined Device 1 is mapped. 0: I/O. 1: Memory. 6:0 Mask.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description Index ECh 7:0 Timer Test Register (R/W) Reset Value: 00h Timer Test Value. The Timer Test register is intended only for test and debug purposes. It is not intended for setting operational timebases. For normal operation, never write to this register.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 4 Description User Defined Device Idle Timer 1 (UDEF1) SMI Status. Indicates whether or not an SMI was caused by expiration of User Defined Device 1 (UDEF1) Idle Timer Count Register (F0 Index A0h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 81h[4] = 1. 3 Keyboard/Mouse Idle Timer SMI Status.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 3 Description Keyboard/Mouse Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the keyboard or mouse. 0: No. 1: Yes. To enable SMI generation, set F0 Index 82h[3] = 1. 2 Parallel/Serial Access Trap SMI Status.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit 2 Description Codec SDATA_IN SMI Status. Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on SDATA_IN. 0: No. 1: Yes. To enable SMI generation, set F0 Index 80h[5] = 1. 1 RTC Alarm (IRQ8#) SMI Status. Indicates whether or not an SMI was caused by an RTC interrupt. 0: No. 1: Yes.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 6.4.1.1 GPIO Support Registers F0 Index 10h, Base Address Register 0 (F0BAR0) points to the base address of where the GPIO runtime and configu- ration registers are located. Table 6-29 gives the bit formats of I/O mapped registers accessed through F0BAR0. Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers Bit Description Offset 00h-03h 31:0 GPDO0 — GPIO Data Out 0 Register (R/W) Reset Value: FFFFFFFFh GPIO Data Out.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued) Bit Description Offset 10h-13h 31:0 GPDO1 — GPIO Data Out 1 Register (R/W) Reset Value: FFFFFFFFh GPIO Data Out. Bits [31:0] of this register correspond to GPIO63-GPIO32 signals, respectively. The value of each bit determines the value driven on the corresponding GPIO signal when its output buffer is enabled.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued) Bit Description 5:0 Signal Select. Selects the GPIO signal to be configured in the Bank selected via bit 5 setting (i.e., Bank 0 or Bank 1). See Table 4-2 on page 70 for GPIO ball muxing options. GPIOs without an associated ball number are not available externally.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued) Bit 4 Description PME Edge/Level Select. Selects the type (edge or level) of the signal that issues a PME from the selected GPIO signal. 0: Edge input. (Default) 1: Level input. For normal operation, always set this bit to 0 (edge input). Erratic system behavior results if this bit is set to 1.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 6.4.1.2 LPC Support Registers F0 Index 14h, Base Address Register 1 (F0BAR1) points to the base address of the register space that contains the configuration registers for LPC support. Table 6-31 gives the bit formats of the I/O mapped registers accessed through F0BAR1. The LPC Interface supports all features described in the LPC bus specification 1.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued) Bit 8 Description IRQ8# Source. Selects the interface source of the IRQ8# signal. 0: ISA - IRQ8# internal signal. (Connected to internal RTC.) 1: LPC - SERIRQ (ball J31). 7 IRQ7 Source. Selects the interface source of the IRQ7 signal. 0: ISA - IRQ7 (unavailable externally). 1: LPC - SERIRQ (ball J31). 6 IRQ6 Source.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued) Bit Description 14 IRQ14 Polarity. If LPC is selected as the interface source for IRQ14 (F0BAR1+I/O Offset 00h[14] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. 13 IRQ13 Polarity. If LPC is selected as the interface source for IRQ13 (F0BAR1+I/O Offset 00h[13] = 1), this bit allows signal polarity selection.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued) Bit 2 Description SMI# Polarity. This bit allows signal polarity selection of the SMI# generated from LPC. 0: Active high. 1: Active low. 1 IRQ1 Polarity. If LPC is selected as the interface source for IRQ1 (F0BAR1+I/O Offset 00h[1] = 1), this bit allows signal polarity selection. 0: Active high. 1: Active low. 0 IRQ0 Polarity.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued) Bit 2 Description DRQ2 Source. Selects the interface source of the DRQ2 signal. 0: ISA - DRQ2 (unavailable externally). 1: LPC - LDRQ# (ball L28). 1 DRQ1 Source. Selects the interface source of the DRQ1 signal. 0: ISA - DRQ1 (unavailable externally). 1: LPC - LDRQ# (ball L28). 0 DRQ0 Source. Selects the interface source of the DRQ0 signal.
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued) Bit 1 Description LPC Serial Port 0 Addressing. Serial Port 0 addresses. See bit 16 for decode. Address selection made via F0BAR1+I/O Offset 14h[4:2]. 0 LPC Parallel Port Addressing. Parallel Port addresses. See bit 16 for decode. Address selection made via F0BAR1+I/O Offset 14h[1:0].
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32581C Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued) Bit Description Offset 18h-1Bh LAD_D1 — LPC Address Decode 1 Register (R/W) Reset Value: 00000000h 31:16 Reserved. Must be set to 0. 15:9 Wide Generic Base Address Select. Defines a 512 byte space. Can be mapped anywhere in the 64 KB I/O space. AC97 and other configuration registers are expected to be mapped to this range.
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Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32581C Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued) Bit 3 Description LPC Timeout Error Status. Indicates whether or not an error was generated by a timeout on LPC. 0: No. 1: Yes. Write 1 to clear. 2 LPC Error Write Status. Indicates whether or not an error was generated during a write operation on LPC. 0: No. 1: Yes. Write 1 to clear. 1 LPC Error DMA Status.
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32581C 6.4.2 Core Logic Module - SMI Status and ACPI Registers - Function 1 SMI Status and ACPI Registers - Function 1 The register space designated as Function 1 (F1) is used to configure the PCI portion of support hardware for the SMI Status and ACPI Support registers. The bit formats for the PCI Header registers are given in Table 6-32.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 6.4.2.1 SMI Status Support Registers F1 Index 10h, Base Address Register 0 (F1BAR0), points to the base address for SMI Status register locations. Table 6-33 gives the bit formats of I/O mapped SMI Status registers accessed through F1BAR0. The registers at F1BAR0+I/O Offset 50h-FFh can also be accessed F0 Index 50h-FFh. The preferred method is to program these registers through the F0 register space. Table 6-33.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit 6 Description SMI Source is a VGA Timer Event. Indicates whether or not an SMI was caused by the expiration of the VGA Timer (F0 Index 8Eh). 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[3] to 1. 5 SMI Source is Video Retrace.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit Description 12 SMI Source is NMI. (Read to Clear) Indicates whether or not an SMI was caused by NMI activity. 0: No. 1: Yes. 11 SMI Source is IRQ2 of SIO Module. (Read to Clear) Indicates whether or not an SMI was caused by IRQ2 of the SIO module. 0: No. 1: Yes. The next level (second level) of SMI status is reported in the SuperI/O module.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit 1 Description SMI Source is Audio Subsystem. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by the audio subsystem. 0: No. 1: Yes. The second level of status is found in F3BAR0+Memory Offset 10h/12h. 0 SMI Source is Power Management Event.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit 0 Description SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI was caused by the expiration of General Purpose Timer 1 (F0 Index 88h). 0: No. 1: Yes. To enable SMI generation, set F0 Index 83h[0] = 1.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit Description Offset 08h-09h 15:0 SMI Speedup Disable Register (Read to Enable) Reset Value: 0000h SMI Speedup Disable. If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register invokes the SMI handler to re-enable Suspend Modulation. The data read from this register can be ignored.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit Description Offset 22h-23h Second Level ACPI PME/SMI Status Register (RC) Reset Value: 0000h The bits in this register contain second level of SMI status reporting. Top level is reported in F1BAR0+I/O Offset 00h/02h[2]. Reading this register clears the status at both the second and top levels.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit 21 Description EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5. 0: No. 1: Yes. To enable SMI generation, set bit 5 to 1. 20 EXT_SMI4 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4. 0: No. 1: Yes. To enable SMI generation, set bit 4 to 1.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit Description 10 EXT_SMI2 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2. 0: No. 1: Yes. To enable SMI generation, set bit 2 to 1. 9 EXT_SMI1 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1. 0: No. 1: Yes. To enable SMI generation, set bit 1 to 1. 8 EXT_SMI0 SMI Status.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued) Bit 0 Description EXT_SMI0 SMI Enable. When this bit is asserted, allow EXT_SMI0 to generate an SMI on negative-edge events. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+00h/02h[10]. Second level SMI status is reported at bits 16 (RC) and 8 (RO).
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 6.4.2.2 ACPI Support Registers F1 Index 40h, Base Address Register 1 (F1BAR1), points to the base address of where the ACPI Support registers are located. Table 6-34 shows the I/O mapped ACPI Support registers accessed through F1BAR1. Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers Bit Description Offset 00h-03h 31:5 P_CNT — Processor Control Register (R/W) Reset Value: 00000000h Reserved. Always reads 0.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit 0 Description PWRBTN_DBNC_DIS (Power Button Debounce). When enabled, a high-to-low or low-to-high transition of greater than 15.8 ms is required on PWRBTN# before it is recognized. 0: Enable. (Default) 1: Disable. (No debounce) Offset 08h-09h PM1A_STS — PM1A Top Level PME/SCI Status Register (R/W) Reset Value: 0000h Notes: 1.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit 4 Description BM_STS (Bus Master Status). Indicates if PME was caused by a system bus master requesting the system bus. 0: No. 1: Yes. For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ch[1] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register.) Write 1 to clear. 3:1 0 Reserved. Must be set to 0.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit Description 13 SLP_EN (Sleep Enable). (Write Only) Allow the system to sequence into the sleeping state associated with the SLP_TYPx (bits [12:10]). 0: Disable. 1: Enable. This is a write only bit and reads of this bit always return a 0. The ACPI state machine always waits for an SMI (any SMI) to be generated and serviced before transitioning into a Sleep state.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit Description Offset 0Fh 7:2 1 ACPI_BIOS_EN Register (R/W) Reset Value: 00h Reserved. Must be set to 0. BIOS_RLS (BIOS Release). (Write Only) When this bit is asserted, allow the BIOS to release control of the global lock. 0: Disable. 1: Enable. This is a write only bit and reads of this bit always return a 0.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit Description 7 Reserved. Must be set to 0. 6 USB_STS. Indicates if PME was caused by a USB interrupt event. 0: No. 1: Yes. Write 1 to clear. For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[6] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this register above.) 5 THRM_STS.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit Description Offset 12h-13h GPE0_EN — General Purpose Event 0 Enable Register (R/W) Reset Value: 0000h In order for the ACPI events described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0] = 1). The SCIs enabled in this register are globally enabled by setting F1BAR1+I/O Offset 0Ch[0] to 1.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit Description Offset 14h 7:4 GPWIO Control Register 1 (R/W) Reset Value: 00h Reserved. Must be set to 0. 3 Reserved. 2 GPWIO2_POL. Select GPWIO2 polarity. 0: Active high 1: Active low 1 GPWIO1_POL. Select GPWIO1 polarity. 0: Active high 1: Active low 0 GPWIO0_POL. Select GPWIO0 polarity.
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Core Logic Module - SMI Status and ACPI Registers - Function 1 32581C Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit Description Offset 16h GPWIO Data Register (R/W) Reset Value: 00h This register contains the direct values of the GPWIO2-GPWIO0 pins. Write operations are valid only for bits defined as outputs. Reads from this register read the last written value if the pin is an output. The pins are configured as inputs or outputs in F1BAR1+I/O Offset 15h. 7:4 Reserved.
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32581C Core Logic Module - SMI Status and ACPI Registers - Function 1 Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued) Bit Description 3:0 SCI_IRQ_ROUTE. SCI is routed to: 0000: Disable 0001: IRQ1 0010: Reserved 0011: IRQ3 0100: IRQ4 0101: IRQ5 0010: IRQ6 0011: IRQ7 1000: IRQ8 1001: IRQ9 1010: IRQ10 1011: IRQ11 1100: IRQ12 1101: IRQ13 1110: IRQ14 1111: IRQ15 For more details see Section 6.2.6.3 "Programmable Interrupt Controller" on page 153.
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32581C Core Logic Module - IDE Controller Registers - Function 2 6.4.3 IDE Controller Registers - Function 2 The register space designated as Function 2 (F2) is used to configure Channels 0 and 1 and the PCI portion of support hardware for the IDE controllers. The bit formats for the PCI Header/Channels 0 and 1 Registers are given in Table 6-35.
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32581C Core Logic Module - IDE Controller Registers - Function 2 Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued) Bit Description Index 30h-3Fh Reserved Index 40h-43h Channel 0 Drive 0 PIO Register (R/W) Reset Value: 00h Reset Value: 00009172h If Index 44h[31] = 0, Format 0. Bits [15:0] configure the same timing control for both command and data. Format 0 settings for a Fast-PCI clock frequency of 33.
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Core Logic Module - IDE Controller Registers - Function 2 32581C Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued) Bit Description Index 44h-47h Channel 0 Drive 0 DMA Control Register (R/W) Reset Value: 00077771h The structure of this register depends on the value of bit 20. If bit 20 = 0, Multiword DMA Settings for a Fast-PCI clock frequency of 33.
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32581C Core Logic Module - IDE Controller Registers - Function 2 Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued) Bit Description Index 50h-53h Channel 1 Drive 0 PIO Register (R/W) Reset Value: 00009172h Channel 1 Drive 0 Programmed I/O Control Register. See F2 Index 40h for bit descriptions. Index 54h-57h Channel 1 Drive 0 DMA Control Register (R/W) Reset Value: 00077771h Channel 1 Drive 0 MDMA/UDMA Control Register.
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32581C Core Logic Module - IDE Controller Registers - Function 2 6.4.3.1 IDE Controller Support Registers F2 Index 20h, Base Address Register 4 (F2BAR4), points to the base address of where the registers for IDE controller configuration are located. Table 6-36 gives the bit for- mats of the I/O mapped IDE Controller Configuration registers that are accessed through F2BAR4. Table 6-36.
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32581C Core Logic Module - IDE Controller Registers - Function 2 Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers (Continued) Bit Description Offset 08h 7:4 3 IDE Bus Master 1 Command Register — Secondary (R/W) Reset Value: 00h Reserved. Must be set to 0. Must return 0 on reads. Read or Write Control. Sets the direction of bus master transfers. 0: PCI reads are performed. 1: PCI writes are performed. This bit should not be changed when the bus master is active. 2:1 0 Reserved.
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32581C Core Logic Module - Audio Registers - Function 3 6.4.4 Audio Registers - Function 3 The register designated as Function 3 (F3) is used to configure the PCI portion of support hardware for the audio registers. The bit formats for the PCI Header registers are given in Table 6-37. A Base Address register (F3BAR0), located in the PCI Header registers of F3, is used for pointing to the register space designated for support of audio, described later in this section. Table 6-37.
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32581C Core Logic Module - Audio Registers - Function 3 6.4.4.1 Audio Support Registers F3 Index 10h, Base Address Register 0 (F3BAR0), points to the base address of where the registers for audio support are located. Table 6-38 gives the bit formats of the memory mapped audio configuration registers that are accessed through F3BAR0. Table 6-38.
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Core Logic Module - Audio Registers - Function 3 32581C Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description 16 Codec Status Valid. (Read Only) Indicates if the status in bits [15:0] of this register is valid. This bit is high during slots 3 to 11 of the AC97 frame (i.e., for approximately 14.5 µs), for every frame. 0: No. 1: Yes. 15:0 Codec Status. (Read Only) This is the codec status data that is received from the codec in slot 2 on SDATA_IN.
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit 4 Description Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 2. 0: No. 1: Yes. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR0+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the Audio Bus Master 2 SMI Status Register (F3BAR0+Memory Offset 31h[0] = 1).
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Core Logic Module - Audio Registers - Function 3 32581C Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit 4 Description Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 2. 0: No. 1: Yes. SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR0+Memory Offset 30h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 31h[0] = 1).
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit 12 Description DMA Trap SMI Status. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the DMA I/O Trap. 0: No. 1: Yes. (See the note included in the general description of this register above.) This is the third level of SMI status reporting. Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit 5 Description Low MPU I/O Trap. If this bit is enabled and an access occurs at I/O Port 300h-301h, an SMI is generated. 0: Disable. 1: Enable. Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1]. Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0]. Third level SMI status is reported at F3BAR0+Memory Offset 14h[11].
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit 7 Description IRQ7 Internal. Configures IRQ7 for internal (software) or external (hardware) use. 0: External. 1: Internal. 6 Reserved. Must be set to 0. 5 IRQ5 Internal. Configures IRQ5 for internal (software) or external (hardware) use. 0: External. 1: Internal. 4 IRQ4 Internal. Configures IRQ4 for internal (software) or external (hardware) use. 0: External.
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Core Logic Module - Audio Registers - Function 3 32581C Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description 20 Mask Internal IRQ4. (Write Only) 0: Disable. 1: Enable. 19 Mask Internal IRQ3. (Write Only) 0: Disable. 1: Enable. 18 Reserved. (Write Only) Must be set to 0. 17 Mask Internal IRQ1. (Write Only) 0: Disable. 1: Enable. 16 Reserved. (Write Only) Must be set to 0. 15 Assert Masked Internal IRQ15. 0: Disable. 1: Enable.
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description 1 Assert Masked Internal IRQ1. 0: Disable. 1: Enable. 0 Reserved. Must be set to 0. Offset 20h Audio Bus Master 0 Command Register (R/W) Reset Value: 00h Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved. Must be set to 0. Must return 0 on reads. 3 Read or Write Control.
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description Offset 28h Audio Bus Master 1 Command Register (R/W) Reset Value: 00h Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4. 7:4 Reserved. Must be set to 0. Must return 0 on reads. 3 Read or Write Control. Set the transfer direction of Audio Bus Master 1. 0: PCI reads are performed. 1: PCI writes are performed.
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description Offset 30h Audio Bus Master 2 Command Register (R/W) Reset Value: 00h Audio Bus Master 2: Output to codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0. Must return 0 on reads. 3 Read or Write Control. Sets the transfer direction of Audio Bus Master 2. 0: PCI reads are performed. 1: PCI writes are performed.
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description Offset 38h Audio Bus Master 3 Command Register (R/W) Reset Value: 00h Audio Bus Master 3: Input from codec; 16-Bit; Slot 5. 7:4 Reserved. Must be set to 0. Must return 0 on reads. 3 Read or Write Control. Sets the transfer direction of Audio Bus Master 3. 0: PCI reads are performed. 1: PCI writes are performed.
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description Offset 40h Audio Bus Master 4 Command Register (R/W) Reset Value: 00h Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[19] selects slot). 7:4 Reserved. Must be set to 0. Must return 0 on reads. 3 Read or Write Control. Set the transfer direction of Audio Bus Master 4. 0: PCI reads are performed.
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32581C Core Logic Module - Audio Registers - Function 3 Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued) Bit Description Offset 48h Audio Bus Master 5 Command Register (R/W) Reset Value: 00h Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] selects slot). 7:4 Reserved. Must be set to 0. Must return 0 on reads. 3 Read or Write Control. Set the transfer direction of Audio Bus Master 5. 0: PCI reads are performed.
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32581C 6.4.5 Core Logic Module - X-Bus Expansion Interface - Function 5 X-Bus Expansion Interface - Function 5 The register space designated as Function 5 (F5) is used to configure the PCI portion of support hardware for accessing the X-Bus Expansion support registers. The bit formats for the PCI Header Registers are given in Table 639.
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Core Logic Module - X-Bus Expansion Interface - Function 5 32581C Table 6-39. F5: PCI Header Registers for X-Bus Expansion (Continued) Bit Description Index 1Ch-1Fh Base Address Register 3 - F5BAR3 (R/W) Reset Value: 00000000h Reserved. Reserved for possible future use by the Core Logic module. Configuration of this register is programmed through the F5BAR3 Mask Register (F5 Index 4Ch). Index 20h-23h Base Address Register 4 - F5BAR4 (R/W) Reset Value: 00000000h Reserved.
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32581C Core Logic Module - X-Bus Expansion Interface - Function 5 Table 6-39. F5: PCI Header Registers for X-Bus Expansion (Continued) Bit Description Index 44h-47h F5BAR1 Mask Address Register (R/W) Reset Value: 00000000h To use F5BAR1, the mask register should be programmed first. The mask register defines the size of F5BAR1 and whether the accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
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Core Logic Module - X-Bus Expansion Interface - Function 5 32581C Table 6-39. F5: PCI Header Registers for X-Bus Expansion (Continued) Bit Description Index 64h-67h Scratchpad: Usually used for Configuration Block Address (R/W) Reset Value: 00000000h BIOS writes a value, of the Configuration Block Address.
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32581C Core Logic Module - X-Bus Expansion Interface - Function 5 6.4.5.1 X-Bus Expansion Support Registers F5 Index 10h, Base Address Register 0 (F5BAR0) set the base address that allows PCI access to additional I/O Con- trol support registers. Table 6-40 shows the support registers accessed through F5BAR0. Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers Bit Description Offset 00h-03h 31:28 27 I/O Control Register 1 (R/W) Reset Value: 010C0007h Reserved.
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Core Logic Module - X-Bus Expansion Interface - Function 5 32581C Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers (Continued) Bit Description Offset 04h-07h 31:2 1 I/O Control Register 2 (R/W) Reset Value: 00000002h Reserved. Write as read. Video Processor Access Enable. Allows access to video processor using F4BAR0. 0: Disable. 1: Enable. (Default) Note: 0 This bit is readable after the register (F5BAR0+Offset 04h) has been written once. IO_STRAP_IDSEL_SELECT (IDSEL Strap Override).
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32581C 6.4.6 Core Logic Module - USB Controller Registers - PCIUSB USB Controller Registers - PCIUSB The registers designated as PCIUSB are 32-bit registers decoded from the PCI address bits [7:2] and C/BE[3:0]#, when IDSEL is high, AD[10:8] select the appropriate function, and AD[1:0] are 00. The PCI Configuration registers are listed in Table 6-41. They can be accessed as any number of bytes within a single 32-bit aligned unit. They are selected by the PCI-standard Index and Byte-Enable method.
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Core Logic Module - USB Controller Registers - PCIUSB 32581C Table 6-41. PCIUSB: USB PCI Configuration Registers (Continued) Bit Description Index 06h-07h Status Register (R/W) Reset Value: 0280h The PCI specification defines this register to record status information for PCI related events. This is a read/write register. However, writes can only reset bits. A bit is reset whenever the register is written and the data in the corresponding bit location is a 1. 15 Detected Parity Error.
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32581C Core Logic Module - USB Controller Registers - PCIUSB Table 6-41.
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Core Logic Module - USB Controller Registers - PCIUSB 32581C Table 6-42. USB_BAR+Memory Offset: USB Controller Registers Bit Description Offset 00h-03h HcRevision Register (RO) Reset Value = 00000110h 31:8 Reserved. Read/Write 0s. 7:0 Revision (Read Only). Indicates the Open HCI Specification revision number implemented by the Hardware. USB supports 1.0 specification. (X.Y = XYh). Offset 04h-07h 31:11 HcControl Register (R/W) Reset Value = 00000000h Reserved. Read/Write 0s.
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32581C Core Logic Module - USB Controller Registers - PCIUSB Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit Description 6 RootHubStatusChange. This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed. 5 FrameNumberOverflow. Set when bit 15 of FrameNumber changes value. 4 UnrecoverableError (Read Only). This event is not implemented and is hard-coded to 0. Writes are ignored. 3 ResumeDetected.
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Core Logic Module - USB Controller Registers - PCIUSB 32581C Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit 6 Description RootHubStatusChangeEnable. 0: Ignore. 1: Disable interrupt generation due to Root Hub Status Change. 5 FrameNumberOverflowEnable. 0: Ignore. 1: Disable interrupt generation due to Frame Number Overflow. 4 UnrecoverableErrorEnable. This event is not implemented. All writes to this bit will be ignored. 3 ResumeDetectedEnable. 0: Ignore.
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32581C Core Logic Module - USB Controller Registers - PCIUSB Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit Description Offset 34h-37h 31 HcFmInterval Register (R/W) Reset Value = 00002EDFh FrameIntervalToggle (Read Only). This bit is toggled by HCD when it loads a new value into FrameInterval. 30:16 FSLargestDataPacket (Read Only). This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. 15:14 Reserved.
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Core Logic Module - USB Controller Registers - PCIUSB 32581C Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit Description 7:0 NumberDownstreamPorts (Read Only). USB supports three downstream ports. Note: This register is only reset by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub. These bit should not be written during normal operation.
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32581C Core Logic Module - USB Controller Registers - PCIUSB Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit Description Offset 54h-57h 31:21 20 HcRhPortStatus[1] Register (R/W) Reset Value = 00000000h Reserved. Read/Write 0s. PortResetStatusChange. This bit indicates that the port reset signal has completed. 0: Port reset is not complete. 1: Port reset is complete. 19 PortOverCurrentIndicatorChange. This bit is set when OverCurrentIndicator changes.
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Core Logic Module - USB Controller Registers - PCIUSB 32581C Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit 1 Description Read: PortEnableStatus. 0: Port disabled. 1: Port enabled. Write: SetPortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect. 0 Read: CurrentConnectStatus. 0: No device connected. 1: Device connected. If DeviceRemoveable is set (not removable) this bit is always 1. Write: ClearPortEnable. Writing 1 a clears PortEnableStatus.
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32581C Core Logic Module - USB Controller Registers - PCIUSB Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit 3 Description Read: PortOverCurrentIndicator. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set. 0: No over-current condition. 1: Over-current condition. Write: ClearPortSuspend. Writing a 1 initiates the selective resume sequence for the port.
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32581C Core Logic Module - USB Controller Registers - PCIUSB Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit 8 Description Read: PortPowerStatus. This bit reflects the power state of the port regardless of the power switching mode. 0: Port power is off. 1: Port power is on. If NoPowerSwitching is set, this bit is always read as 1. Write: SetPortPower. Writing a 1 sets PortPowerStatus. Writing a 0 has no effect. 7:5 Reserved. Read/Write 0s. 4 Read: PortResetStatus.
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32581C Core Logic Module - USB Controller Registers - PCIUSB Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued) Bit Description 1 EmulationInterrupt (Read Only). This bit is a static decode of the emulation interrupt condition. 0 EmulationEnable. When set to 1 the HC is enabled for legacy emulation and will decode accesses to I/O registers 60h and 64h and generate IRQ1 and/or IRQ12 when appropriate.
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32581C Core Logic Module - ISA Legacy Register Space 6.4.7 ISA Legacy Register Space The ISA Legacy registers reside in the ISA I/O address space in the address range from 000h to FFFh and are accessed through typical input/output instructions (i.e., CPU direct R/W) with the designated I/O port address and 8-bit data.
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32581C Core Logic Module - ISA Legacy Register Space Table 6-43. DMA Channel Control Registers (Continued) Bit 2 Description Channel 2 Terminal Count. Indicates if TC was reached. 0: No. 1: Yes. 1 Channel 1 Terminal Count. Indicates if TC was reached. 0: No. 1: Yes. 0 Channel 0 Terminal Count. Indicates if TC was reached. 0: No. 1: Yes. Write 7 DMA Command Register, Channels 3:0 DACK Sense. 0: Active low. 1: Active high. 6 DREQ Sense. 0: Active high. 1: Active low. 5 Write Selection.
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Core Logic Module - ISA Legacy Register Space 32581C Table 6-43. DMA Channel Control Registers (Continued) Bit Description I/O Port 00Bh 7:6 00: 01: 10: 11: 5 DMA Channel Mode Register, Channels 3:0 (WO) Transfer Mode. Demand. Single. Block. Cascade. Address Direction. 0: Increment. 1: Decrement. 4 Auto-initialize. 0: Disable. 1: Enable. 3:2 Transfer Type. 00: 01: 10: 11: 1:0 Verify. Write transfer (I/O to memory). Read transfer (memory to I/O). Reserved. Channel Number Mode Select.
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32581C Core Logic Module - ISA Legacy Register Space Table 6-43. DMA Channel Control Registers (Continued) Bit Description I/O Port 0D0h (R/W) Read Note: 7 DMA Status Register, Channels 7:4 Channels 5, 6, and 7 are not supported. Channel 7 Request. Indicates if a request is pending. 0: No. 1: Yes. 6 Channel 6 Request. Indicates if a request is pending. 0: No. 1: Yes. 5 Channel 5 Request. Indicates if a request is pending. 0: No. 1: Yes. 4 Undefined. 3 Channel 7 Terminal Count.
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Core Logic Module - ISA Legacy Register Space 32581C Table 6-43. DMA Channel Control Registers (Continued) Bit Description I/O Port 0D2h Note: 7:3 2 Software DMA Request Register, Channels 7:4 (W) Channels 5, 6, and 7 are not supported. Reserved. Must be set to 0. Request Type. 0: Reset. 1: Set. 1:0 Channel Number Request Select. 00: 01: 10: 11: Illegal. Channel 5. Channel 6. Channel 7. I/O Port 0D4h Note: 7:3 2 DMA Channel Mask Register, Channels 7:4 (WO) Channels 5, 6, and 7 are not supported.
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32581C Core Logic Module - ISA Legacy Register Space Table 6-43. DMA Channel Control Registers (Continued) Bit Description I/O Port 0DEh Note: DMA Write Mask Register Command, Channels 7:4 (W) Channels 5, 6, and 7 are not supported. Table 6-44. DMA Page Registers Bit Description I/O Port 081h DMA Channel 2 Low Page Register (R/W) Address bits [23:16] (byte 2). I/O Port 082h DMA Channel 3 Low Page Register (R/W) Address bits [23:16] (byte 2).
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32581C Core Logic Module - ISA Legacy Register Space Table 6-45. Programmable Interval Timer Registers Bit Description I/O Port 040h Write 7:0 PIT Timer 0 Counter Counter Value. Read PIT Timer 0 Status 7 Counter Output. State of counter output signal. 6 Counter Loaded. Indicates if the last count written is loaded. 0: Yes. 1: No. 5:4 Current Read/Write Mode. 00: 01: 10: 11: 3:1 0 Counter latch command. R/W LSB only. R/W MSB only. R/W LSB, followed by MSB. Current Counter Mode. 0-5. BCD Mode.
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32581C Core Logic Module - ISA Legacy Register Space Table 6-45. Programmable Interval Timer Registers (Continued) Bit Description I/O Port 042h Write 7:0 PIT Timer 2 Counter (Speaker) Counter Value. Read PIT Timer 2 Status (Speaker) 7 Counter Output. State of counter output signal. 6 Counter Loaded. Indicates if the last count written is loaded. 0: Yes. 1: No. 5:4 Current Read/Write Mode. 00: 01: 10: 11: 3:1 0 Counter latch command. R/W LSB only. R/W MSB only. R/W LSB, followed by MSB.
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Core Logic Module - ISA Legacy Register Space 32581C Table 6-46. Programmable Interrupt Controller Registers Bit Description I/O Port 020h / 0A0h Master / Slave PIC ICW1 (WO) 7:5 Reserved. Must be set to 0. 4 Reserved. Must be set to 1. 3 Trigger Mode. 0: Edge. 1: Level. 2 Vector Address Interval 0: 8 byte intervals. 1: 4 byte intervals. 1 Reserved. Must be set to 0 (cascade mode). 0 Reserved. Must be set to 1 (ICW4 must be programmed).
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32581C Core Logic Module - ISA Legacy Register Space Table 6-46. Programmable Interrupt Controller Registers (Continued) Bit 2 Description IRQ2 / IRQ10 Mask. 0: Not Masked. 1: Mask. 1 IRQ1 / IRQ9 Mask. 0: Not Masked. 1: Mask. 0 IRQ0 / IRQ8 Mask. 0: Not Masked. 1: Mask. I/O Port 020h / 0A0h 7:5 Master / Slave PIC OCW2 (WO) Rotate/EOI Codes. 000: Clear rotate in Auto EOI mode 001: Non-specific EOI 010: No operation 011: Specific EOI (bits [2:0] must be valid) 4:3 Reserved. Must be set to 0.
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Core Logic Module - ISA Legacy Register Space 32581C Table 6-46. Programmable Interrupt Controller Registers (Continued) Bit 3 Description IRQ3 / IRQ11 Pending. 0: Yes. 1: No. 2 IRQ2 / IRQ10 Pending. 0: Yes. 1: No. 1 IRQ1 / IRQ9 Pending. 0: Yes. 1: No. 0 IRQ0 / IRQ8 Pending. 0: Yes. 1: No. Interrupt Service Register 7 IRQ7 / IRQ15 In-Service. 0: No. 1: Yes. 6 IRQ6 / IRQ14 In-Service. 0: No. 1: Yes. 5 IRQ5 / IRQ13 In-Service. 0: No. 1: Yes. 4 IRQ4 / IRQ12 In-Service. 0: No. 1: Yes.
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32581C Core Logic Module - ISA Legacy Register Space Table 6-47. Keyboard Controller Registers Bit Description I/O Port 060h External Keyboard Controller Data Register (R/W) Keyboard Controller Data Register. All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port assert the A20M# signal or cause a warm CPU reset.
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32581C Core Logic Module - ISA Legacy Register Space Table 6-48. Real-Time Clock Registers Bit Description I/O Port 070h RTC Address Register (WO) This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Index BBh). 7 NMI Mask. 0: Enable. 1: Mask. 6:0 RTC Register Index. A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
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32581C Core Logic Module - ISA Legacy Register Space Table 6-49. Miscellaneous Registers (Continued) Bit 3 Description IRQ3 Edge or Level Sensitive Select. Selects PIC IRQ3 sensitivity configuration. 0: Edge. 1: Level. 2:0 Reserved. Must be set to 0. I/O Port 4D1h Interrupt Edge/Level Select Register 2 (R/W) Reset Value: 00h Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits 7:6 and 4:1 in this register. 2.
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Video Processor Module 32581C 7 7.0Video Processor Module The Video Processor module contains a high performance video back-end accelerator, a video/graphics Mixer/ Blender, a Video Input Port (VIP), supporting a TFT interface. The back-end accelerator functions include horizontal and vertical scaling and filtering of the video stream. The Mixer/Blender function includes color space conversion, gamma correction, and mixing or alpha blending the video and graphics streams.
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32581C 7.1 Video Processor Module Module Architecture Figure 7-1 shows a top-level block diagram of the Video Processor. For information about the relationship between the Video Processor and the other modules of the SC3200, see Section 2.2 on page 22.
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Video Processor Module 7.2 Functional Description To understand why the Video Processor functions as it does, it is first important to understand the difference between video and graphics. Video is pictures in motion, which usually starts out in an encoded format (i.e., MPEG2, AVI, MPEG4) or is a TV broadcast. These pictures or frames are generally dynamic and are drawn 24 to 30 frames per second. Conversely, graphic data is relatively static and is drawn - usually using hardware accelerators.
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32581C Video Processor Module Vertical Retrace - Logical Lines 4-9 — Scan Lines 4-9 (Not normally User Data) Vertical Retrace - Logical Lines 10-21 — Scan lines 10-21 (Nominal VBI Lines) Vertical Retrace - Logical Lines 22, 23 — Scan lines 22, 23 VBI_Total_Count_Odd (Not normally User Data) Active Video Logical Line 24 — Scan Lines 24-263 Vertical Retrace - Logical Line 24 — Scan Line 1 VBI_Line_Offset_Odd Vertical Retrace - Logical Lines 2, 3 — Scan Lines 2, 3 (Not normally User Data) VSYNC Start
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32581C Video Processor Module 7.2.1 Video Input Port (VIP) The VIP block is designed to interface the SC3200 with external video processors (e.g., Philips PNX1300 or Sigma Designs EM8400) or external TV decoders (e.g., Philips SAA7114). It inputs CCIR-656 Video and raw VBI data sourced by those devices, decodes the data, and delivers the data directly to the Video Formatter (Direct Video mode) or to the GX1 module’s video frame buffer (Capture Video/VBI modes).
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32581C The GenLock control hardware is used to synchronize the video input’s field with the GX1 module’s graphics frame. The graphics data is always sent full frame. For the GenLock function to perform correctly, the GX1 module’s Display Controller must be programmed to have a slightly faster frame time then the video input’s field time. This is best accomplished by programming the GX1 module’s Display Controller with a few less (three to five) horizontal lines then the VIP interface.
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32581C Video Processor Module Video Data Odd Base (F4BAR2+Memory Offset 20h) Address not changed during runtime Video Data Even Base (F4BAR2+Memory Offset 24h) Address not changed during runtime Odd Field Even Field DC_VID_ST_OFFSET (GX_BASE+Memory Offset 8320h) Ping-pongs between the two buffers during runtime GX1 Module’s Video Frame Buffer 30 frames per second Buf #1 Capture video fill sequence Video subsystem empty sequence 1 2 1 3 2 3 4 5 4 5 6 6 7 7 8 9 10 11 12 13 14 15
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32581C 3) Video Processor Module Field Interrupt. 7.2.1.3 Capture VBI Mode There are three types of VBI data defined by the CCIR-656 protocol: Task A data, Task B data, and Ancillary data. The VIP block supports the capture for each data type. Generally Task A data is the data type captured. Just as in Capture Video mode, there are three registers that tell the bus master where to put the raw VBI data in the GX1 module’s frame buffer.
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32581C Video Processor Module 7.2.2 Video Block The Video block receives video data from the VIP block or the GX1 module’s video frame buffer. The video data is formatted and scaled and then sent to the Mixer/Blender. The video data also changes clock domains while in the Video block. It is clocked in with the GX1 module’s video clock and it is clocked out with the GX1 module’s graphics clock. A diagram of the Video block is shown in Figure 7-7. 7.2.2.
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32581C Video Processor Module 7.2.2.2 Horizontal Downscaler with 4-Tap Filtering The Video Processor implements up to 8:1 horizontal downscaling with 4-tap filtering for horizontal interpolation. Filtering is performed on video data input to the Video Processor. This data is fed to the filter and then to the downscaler. There is a bypass path for both filtering and downscaling logic. If this bypass is enabled, video data is written directly into the line buffers. (See Figure 7-8.
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32581C Video Processor Module 7.2.2.3 Line Buffers After the data has been optionally horizontally downscaled the video data is stored in a 3-line buffer. Each line is 360 DWORDs, which means a line width of up to 720 pixels can be stored. This buffer supports two functions. First, the clock domain of the video data changes from the GX1 module’s video clock to the GX1 module’s graphics clock.
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32581C 7.2.3 Video Processor Module Mixer/Blender Block The Mixer/Blender block of the Video Processor module performs all the necessary functions to properly mix/blend the video data and the graphics data. These functions include Color Space Conversion (CSC), optional Gamma correction, color/chroma key, and the mixing/blending logic. See Figure 7-10 for block diagram of the Mixer/Blender Block. Video/Graphics mixing/blending must be performed in the RGB format. The YUV to RGB CSC (Section 7.2.3.
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32581C Video Processor Module Table 7-1. Valid Mixing/Blending Configurations Flicker Mixing/Blending1 (Bit) Filter2 (Bit) 13 11 10 9 30 29 Mode Comment 0 0 1 0 0 0 Input: YUV Progressive Video • Produces highest quality RGB output (see Section 7.2.1.2 "Capture Video Mode", Weave subsection on page 315). • Produces highest quality RGB output (see Section 7.2.1.2 "Capture Video Mode", Weave subsection on page 315). • Not supported. • Not supported. • Typically Direct Video mode.
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32581C Video Processor Module 7.2.3.4 Color/Chroma Key and Mixer/Blender The Mixer/Blender takes each pixel of the graphics and video data streams and mixes or blends them together. Mixing is simply choosing the graphics pixel or the video pixel. Blending takes a percentage of a graphics pixel (Alpha_value * Graphics_pixel_value) and percentage of the video pixel (1 - Alpha_Value * Video_pixel_value) and adds them together. The percentages of each add up to 100%. The actual formula is: PAL).
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32581C Video Processor Module Mixing/Blending Operation Table 7-2 on page 323 shows the truth table used to create the flow diagram, Figure 7-12 on page 324, that the Mixer/ Blender logic uses to determine each pixels disposition. Table 7-2.
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32581C Video Processor Module Start Use selected cursor color for pixel Yes Cursor color key matches graphics value No Use graphics value for this pixel Yes Pixel outside the video window No Pixel inside1 alpha window No “Graphics2 inside Video” is enabled Yes Blend graphics values and video values using the alpha value for this window No No Pixel value3 matches normal color key Pixel value3 matches normal color key Yes Color register enabled for this window COLOR_CHROMA _SEL = 1 No COLO
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81C Video Processor Module 7.2.4 TFT Interface • TFTDCK - data clock signal. The TFT interface can be programmed to one of two sets of balls: IDE balls or Parallel Port balls. PMR[23] of the General Configuration registers program where the TFT interface exists (see Table 4-2 on page 70). Note: If the TFT interface is on the IDE balls, the maximum FPCLK supported is 40 MHz. If the TFT interface is on the Parallel Port balls the maximum FPCLK supported is 80 MHz.
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32581C 7.2.5 Video Processor Module Integrated PLL The integrated PLL can generate frequencies up to 135 MHz from a single 27 MHz source. The clock frequency is programmable using two registers. Figure 7-14 shows the block diagram of the Video Processor integrated PLL. FREF is 27 MHz, generated by an external crystal and an integrated oscillator.
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32581C Video Processor Module - Register Summary 7.3 Register Descriptions The register space for accessing and configuring the Video Processor is located in the Core Logic Chipset Register Space (F0-F5). The Chipset Register Space is accessed via the PCI interface using the PCI Type One Configuration Mechanism (see Section 6.3.1 "PCI Configuration Space and Access Methods" on page 173). 7.3.1 Register Summary The tables in this subsection summarize the registers of the Video Processor.
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32581C Video Processor Module - Register Summary Table 7-4.
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Video Processor Module - Register Summary 32581C Table 7-5.
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32581C 7.3.2 Video Processor Module - Video Processor Registers - Function 4 Video Processor Registers - Function 4 The register space designated as Function 4 (F4) is used to configure the PCI portion of support hardware for accessing the Video Processor support registers, including VIP (separate BAR). The bit formats for the PCI Header registers are given in Table 7-6.
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-6. F4: PCI Header Registers for Video Processor Support Registers (Continued) Bit Description Index 3Dh Interrupt Pin Register (R/W) Reset Value: 03h This register selects which interrupt pin the device uses. VIP uses INTC# after reset. INTA#, INTB# or INTD# can be selected by writing 1, 2 or 4, respectively.
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32581C Video Processor Module - Video Processor Registers - Function 4 7.3.2.1 Video Processor Support Registers - F4BAR0 F4 Index 10h, Base Address Register 0 (F4BAR0) sets the base address that allows PCI access to the Video Processor support registers, not including VIP. A separate base address register (F4BAR2) is used to access VIP support registers (see Section 7.3.2.2 on page 345).
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit 0 Description VID_EN (Video Enable). Enables video acceleration hardware. 0: Disable (reset) video module. 1: Enable. Offset 04h-07h Display Configuration Register (R/W) Reset Value: x0000000h General configuration register for display control.
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 08h-0Bh Video X Position Register (R/W) Reset Value: 00000000h Provides the window X position. This register is programmed relative to CRT horizontal sync input (not physical screen position).
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 14h-17h Video Color Key Register (R/W) Reset Value: 00000000h Provides the video color key. The color key can be used to allow irregular shaped overlays of graphics onto video, or video onto graphics, within a scaled video window. 31:24 Reserved. 23:0 VID_CLR_KEY (Video Color Key).
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 28h-2Bh Miscellaneous Register (R/W) Reset Value: 00001400h Configuration and control register for miscellaneous characteristics of the Video Processor. 31:13 12 Reserved. PLL2_PWR_EN (PLL2 Power-Down Enable). 0: Power-down. 1: Normal. 11:10 9:1 0 Reserved. Set to 1. Reserved. GAMMA_EN (Gamma Correction RAM Enable).
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 3Ch-3Fh Video Downscaler Control Register (R/W) Reset Value: 00000000h Controls the characteristics of the integrated video downscaler. 31:7 6 Reserved DTS (Downscale Type Select). 0: Type A (Downscale formula is 1/m+1, m pixels are dropped, 1 pixel is kept).
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 4Ch-4Fh Video De-Interlacing and Alpha Control Register (R/W) Reset Value: 00060000h 31:22 Reserved. 21:20 ALPHA3_WIN_PRIORITY (Alpha Window 3 Priority). Determines the priority of Alpha Window 3. A higher number indicates a higher priority. Priority is used to determine display order for overlapping alpha windows.
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit 8 Description GFX_INS_VIDEO (Graphics Inside Video). This bit works in conjunction with bit COLOR_CHROMA_SEL (F4BAR0+Memory Offset 4Ch[20]). COLOR_CHROMA_SEL selects whether the graphics is used for color keying or the video data stream is used for chroma keying. If COLOR_CHROMA_SEL = 0, graphics data is compared to the color key.
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 60h-63h Note: Alpha Window 1 X Position Register (R/W) Reset Value: 00000000h H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively).
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 70h-73h Note: Alpha Window 2 X Position Register (R/W) Reset Value: 00000000h H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively).
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 80h-83h Alpha Window 3 X Position Register (R/W) Reset Value: 00000000h Note: H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers (GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively).
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 90h-93h Video Request Register (R/W) Reset Value: 001B0017h 31:28 Reserved. Set to 0. 27:16 VIDEO_X_REQ (Video Horizontal Request). Determines the horizontal (pixel) location at which to start requesting video data out of the video FIFO.
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued) Bit Description Offset 420h-423h 31:24 GenLock Register (R/W) Reset Value: 00000000h Reserved. Must be set to 0. 23 ODD_TO (Odd Field Time Out). Indicates CGENTO0 (F4BAR0+Memory Offset 43Ch[15:0]) has expired. This bit can be reset by writing 1 to it. 22 EVEN_TO (Even Field Time Out).
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32581C Video Processor Module - Video Processor Registers - Function 4 7.3.2.2 VIP Support Registers - F4BAR2 F4 Index 18h, Base Address Register 2 (F4BAR2) points to the base address of where the VIP Configuration registers are located. Table 7-8 shows the memory mapped VIP support registers accessed through F4BAR2. Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers Bit Description Offset 00h-03h 31:23 22 Video Interface Port Configuration Register (R/W) Reset Value: 00000000h Reserved.
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers (Continued) Bit Description 10 Auto-Flip. Video port operation mode. 0: The video port automatically detects the even and odd fields based on the VP_HREF and VP_VSYNC_IN signals or the CCIR656 control codes. 1: The even/odd field detect logic is disabled and the video port automatically toggles between the even and odd buffers during capture.
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Video Processor Module - Video Processor Registers - Function 4 32581C Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers (Continued) Bit 8 Description Video Data Capture Active. (Read Only) 0: Video data is not being stored to memory. 1: Video data is now being stored to memory. 7:1 0 Reserved. (Read Only) Run Status. (Read Only) 0: Video port capture is not active. 1: Video port capture is in progress.
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32581C Video Processor Module - Video Processor Registers - Function 4 Table 7-8. F4BAR2+Memory Offset: VIP Configuration Registers (Continued) Bit Description Offset 40h-43h VBI Data Odd Base Register (R/W) Reset Value: 00000000h This register specifies the base address in graphics memory where VBI data for odd fields are stored. Changes to this register take effect at the beginning of the next field. The value in this register is 16-byte aligned. Note: 31:0 This register is double-buffered.
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Debugging and Monitoring 32581C 8 8.0Debugging and Monitoring 8.1 Testability (JTAG) The Test Access Port (TAP) allows board level interconnection verification and chip production tests. An IEEE1149.1a compliant test interface, TAP supports all IEEE mandatory instructions as well as several optional instructions for added functionality. See Table 8-1 • for a summary of all instructions support. For further information on JTAG, refer to IEEE Standard 1149.
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32581C 350 Debugging and Monitoring AMD Geode™ SC3200 Processor Data Book
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Electrical Specifications 32581C 9 9.0Electrical Specifications 9.1.2 This chapter provides information about: • General electrical specifications Power/Ground Connections and Decoupling • AC characteristics When testing and operating the SC3200, use standard high frequency techniques to reduce parasitic effects. For example: All voltage values in this chapter are with respect to VSS unless otherwise noted. • Filter the DC power leads with low-inductance decoupling capacitors.
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32581C 9.1.4 Electrical Specifications Operating Conditions Table 9-3 lists the various power supplies of the SC3200 and provides the device operating conditions. Table 9-3. Operating Conditions Symbol (Note 1) Parameter TC Operating case temperature AVCCUSB Min Typ Max Unit 0 - 85 Analog power supply. Powers internal analog circuits and some external signals (see Table 9-4). 3.14 3.3 3.46 V VBAT Battery supply voltage. Powers RTC and ACPI when VBAT is greater than VSB (by at least 0.
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32581C Electrical Specifications Table 9-4 indicates which power rails are used for each signal of the SC3200 external interface. Power planes not listed in this table are internal, and are not related to signals of the external interface. Table 9-4.
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32581C Electrical Specifications 9.1.5.3 Definition of System Conditions for Measuring On Parameters The SC3200’s current is highly dependent on two functional characteristics, DCLK (DOT clock) and SDRAM frequency. Table 9-5 shows how these factors are controlled when measuring the typical average and absolute maximum processor current parameters. 9.1.5.4 DC Current Measurements Table 9-6 and Table 9-7 show the DC current measurements of the SC3200. Table 9-5.
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32581C Electrical Specifications Table 9-7. DC Characteristics for Active Idle, Sleep, and Off States Symbol ParameterNote 1 Min Typ Max ICC3IDLE fCLK = 233 MHz, I/O Current @ VIO = 3.3V (Nominal); CPU state = Active Idle 260 fCLK = 266 MHz, I/O Current @ VIO = 3.3V (Nominal); CPU state = Active Idle 270 ICC3SLP I/O Current @ VIO = 3.3V (Nominal); CPU state = Sleep 20 ICOREIDLE fCLK = 233 MHz, Core Current @ VCORE = 1.
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32581C 9.1.7 Electrical Specifications Pull-Up and Pull-Down Resistors Note: The following table lists input balls that are internally connected to a pull-up (PU) or pull-down (PD) resistor. If these balls are not used, they do not require connection to an external PU or PD resistor. The resistors described in this table are implemented as transistors. The resistance for PUs assumes VIN = VSS and for PDs assumes VIN = VIO. Table 9-9. Balls with PU/PD Resistors Ball No.
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32581C Electrical Specifications 9.2 DC Characteristics Table 9-10 describes the signal buffer types of the SC3200. (See Table 3-2 "BGD432 Ball Assignment - Sorted by Ball Number" on page 29 and Table 3-2 "BGU481 Ball Assignment - Sorted by Ball Number" on page 29) for each signal’s buffer type.) The subsections that follows provide detailed DC characteristics according to buffer type. Table 9-10. Buffer Types Symbol Description Reference Diode Diodes only, no buffer INAB Input, ACCESS.
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32581C 9.2.1 Electrical Specifications INAB DC Characteristics Symbol Parameter Min VIH Input High Voltage 1.4 VIL Input Low Voltage -0.5 (Note 1) IIL Input Leakage Current VHIS Input hysteresis Max Unit Comments V 0.8 V 10 µA VIN = VIO -10 µA VIN = VSS 150 mV Note 1. Not 100% tested. 9.2.2 INBTN DC Characteristics Symbol Parameter Min Max Unit VIH Input High Voltage 2.0 VSB+0.3 (Note 1) V VIL Input Low Voltage -0.5 (Note 1) 0.
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32581C Electrical Specifications 9.2.4 INSTRP DC Characteristics Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIL Input Leakage Current Min Max Unit Comments 0.6VIO VIO+0.3 (Note 1) V 0.3VIO V 36 µA During Reset: VIN = VIO −10 µA VIN = VSS Comments Note 1. Not 100% tested. 9.2.5 INT DC Characteristics Symbol Parameter Min Max Unit VIH Input High Voltage 2.0 VIO+0.3 (Note 1) V VIL Input Low Voltage -0.5 (Note 1) 0.
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32581C 9.2.8 Electrical Specifications INUSB DC Characteristics Symbol Parameter Min Max Unit VIH Input High Voltage 2.0 VIO+0.3 (Note 1) V VIL Input Low Voltage -0.5 (Note 1) 0.8 V IIL Input Leakage Current 10 µA VIN = VIO -10 µA VIN = VSS V |(D+)-(D-)| and Figure 9-1 Includes VDI Range VDI Differential Input Sensitivity 0.2 VCM Differential Common Mode Range 0.8 2.5 V VSE Single Ended Receiver Threshold 0.8 2.0 V Comments Note 1. Not 100% tested.
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32581C Electrical Specifications 9.2.11 ODPCI DC Characteristics Symbol Parameter VOL Output Low Voltage 9.2.12 Min Unit Comments 0.1VIO V Max Unit Comments V lOH = -p mA 0.4 V lOL = n mA Max Unit Comments lOL = 1500 μA Op/n DC Characteristics Symbol Parameter Min VOH Output High Voltage 2.4 VOL Output Low Voltage 9.2.13 Max OPCI DC Characteristics Symbol Parameter VOH Output High Voltage VOL Output Low Voltage 9.2.
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32581C 9.3 Electrical Specifications AC Characteristics The tables in this section list the following AC characteristics: Table 9-11. Default Levels for Measurement of Switching Parameters Symbol • Output delays Parameter Value (V) • Input setup requirements VREF Reference Voltage 1.5 • Input hold requirements VIHD Input High Drive Voltage 2.0 • Output float delays VILD Input Low Drive Voltage 0.8 • Power-up sequencing requirements VOHD Output High Drive Voltage 2.
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32581C Electrical Specifications 9.3.1 Memory Controller Interface The minimum input setup and hold times described in Figure 9-3 (legend C and D) define the smallest acceptable sampling window during which a synchronous input signal must be stable to ensure correct operation.
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32581C Electrical Specifications Table 9-12. Memory Controller Timing Parameters Symbol Parameter Min Max Unit t1 Control output valid from SDCLK[3:0] -3.0 + (x * y) 0.1 + (x * y) ns Note 1, Note 2 t2 MA[12:0], BA[1.0] output valid from SDCLK[3:0] -3.2 + (x * y) 0.1 + (x * y) ns Note 2 t3 MD[63.0] output valid from SDCLK[3:0] -2.2 + (x * y) 0.7 + (x * y) ns Note 2 t4 MD[63.0] read data in setup to SDCLK_IN 1.3 ns t5 MD[63:0] read data hold to SDCLK_IN 2.
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32581C Electrical Specifications t6 t10 t1, t2, t3 t11 VOHD VREF VOLD SDCLK[3:0] t7 Control Output, MA[12:0] BA[1:0], MD[63:0] t7 VREF Figure 9-4. Memory Controller Output Valid Timing Diagram VIHD VREF VILD SDCLK_IN t9 t4 t5 MD[63:0] Data Valid t4 t9 t5 Data Valid Read Data In Figure 9-5.
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32581C 9.3.2 Electrical Specifications Video Port Table 9-13. Video Input Port Timing Parameters Symbol Parameter Min Max Unit tVP_C VPCKIN cycle time 18 ns tVP_S Video Port input setup time before VPCKIN rising edge 6 ns tVP_H Video Port input hold time after VPCKIN rising edge 0 ns tVPCK_FR VPCKIN fall/rise time - tVPCK_D VPCKIN duty cycle 2 ns 35/65 Comments Note 1 % Note 1. Guaranteed by characterization.
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32581C Electrical Specifications 9.3.3 TFT Interface Table 9-14. TFT Timing Parameters Symbol Parameter Min Max Unit tOV TFTD[17:0], TFTDE valid time after TFTDCK rising edge (multiplexed on IDE) 0 8 ns tOV TFTD[17:0], TFTDE valid time after TFTDCK rising edge (multiplexed on Parallel Port) 0 4 ns tCLK_RF TFTDCK rise/fall time between 0.8V and 2.
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32581C 9.3.4 Electrical Specifications ACCESS.bus Interface The following tables describe the timing for the ACCESS.bus signals. Notes: 1) All ACCESS.bus timing is not 100% tested. 2) In this table tCLK = 1/24MHz = 41.7 ns. Table 9-15. ACCESS.
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32581C Electrical Specifications Table 9-16. ACCESS.bus Output Timing Parameters (Continued) Symbol Parameter tSDAfo Min Max Unit AB1D/AB2D signal fall time 300 ns tSDAro AB1D/AB2D signal rise time 1 μs tSDAho AB1D/AB2D hold time tSDAvo AB1D/AB2D valid time 7 * tCLK - tSCLfo Comments After AB1C/AB2C falling edge 7 * tCLK + tRD After AB1C/AB2C falling edge Note 1. K is determined by bits [7:1] of the ACBCTL2 register (LDN 05h/06h, Offset 05h). Note 2.
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32581C Electrical Specifications Start Condition AB1D AB2D AB1C AB2C tDHCsi tDHCso tCSTRsi tCSTRso tCSTRhi tCSTRho Figure 9-10. ACB Start Condition Timing Diagram AB1D AB2D tSDAhi tSDAho tSDAsi tSDAso AB1C AB2C tSDAvo tSDAho tSCLlowi tSCLlowo tSCLhighi tSCLhigho Figure 9-11.
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32581C Electrical Specifications 9.3.5 PCI Bus Interface The SC3200 is compliant with PCI Bus Rev. 2.1 specifications. Relevant information from the PCI Bus specifications is provided below. All parameters in Table 9-17 are not 100% tested. The parameters in this table are further described in Figure 913. Table 9-17. PCI AC Specifications Symbol Parameter Min IOH(AC) (Note 1) Switching current high Max Unit Comments -12VIO mA 0 < VOUT ≤ 0.3VIO, -17.1(VIO-VOUT) mA 0.3VIO < VOUT < 0.
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32581C Electrical Specifications Output Voltage Volts Output Voltage Volts Pull-Up VIO Test Point 0.9 VIO AC Drive Point 0.6 VIO DC Drive Point DC Drive Point 0.3 VIO Pull-Down AC Drive Point -0.5 0.5VIO 0.1 VIO -12VIO -48VIO IOH mA Test Point 1.5 16VIO 64VIO Equation A Equation B IOH = (98.0/VIO)*(VOUT-VIO)*(VOUT+0.4VIO) for VIO>VOUT>0.7VIO IOL = (256/VIO)*VOUT*(VIO-VOUT) for 0V
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32581C Electrical Specifications Table 9-18. PCI Clock Parameters Symbol Parameter Min Max Unit Comments tCYC PCICLK cycle time 30 ns Note 1 tHIGH PCICLK high time 11 ns Note 2 tLOW PCICLK low time 11 ns Note 2 PCICLKsr PCICLK slew Rate 1 4 V/ns Note 3 PCIRSTsr PCIRST# slew Rate 50 - mV/ns Note 4 Note 1. Clock frequency is between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz are not 100% tested.
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32581C Electrical Specifications Table 9-19.
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32581C Electrical Specifications 9.3.5.1 Measurement and Test Conditions Table 9-20. Measurement Condition Parameters Symbol Value Unit VTH 0.6 VIO V Note 1 VTL 0.2 VIO V Note 1 VTEST 0.4 VIO V VSTEP (rising edge) 0.285 VIO V VSTEP (falling edge) 0.615 VIO V 0.4 VIO V 1 V/ns VMAX Input signal edge rate Comments Note 2 Note 1. The input test is performed with 0.1 VIO of overdrive. Timing parameters must not exceed this overdrive. Note 2.
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32581C Electrical Specifications VTH PCICLK VTEST VTL tH tSU VTH VTEST Input Input Valid VTEST VMAX VTL Figure 9-17. Input Timing Measurement Conditions POWER VIO tFAIL PCICLK 100 ms (typ) POR# )( tRST PCIRST# )( tRST-CLK tRST-OFF PCI Signals Note: TRI_STATE The value of tFAIL is 500 ns (maximum) from the power rail which exceeds specified tolerance by more than 500 mV. Figure 9-18.
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32581C Electrical Specifications 9.3.6 Sub-ISA Interface All output timing is guaranteed for 50 pF load, unless otherwise specified. The ISA Clock divisor (defined in F0 Index 50h[2:0] of the Core Logic module) is 011. Table 9-21.
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32581C Electrical Specifications Table 9-21.
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32581C Electrical Specifications tIOCSA tIOCSH ROMCS#/DOCCS# IOCS[1:0]# Valid A[23:0]/BHE# tARx IOR#/RD#/TRDE# MEMR#/DOCR# Valid tRDx tRCUx tRA IOW#/WR# MEMW#/DOCW# tRVDS Valid Data D[15:0] (Read) tRDH tHZ tWDAR D[15:0] (Write) IOCHRDY tRDYAx Note: tRDYH x indicates a numeric index for the relevant symbol. Figure 9-19.
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32581C Electrical Specifications tIOCSA tIOCSH DOCCS#/ROMCS# IOCS[1:0]# Valid A[23:0]/BHE# tAWx Valid tWRx IOW#/WR# MEMW#/DOCW# tWCUx tWA TRDE# tDVx tWTR Valid Data D[15:0] tDH tDF IOCHRDY tRDYAx tRDYH IOR#/RD# MEMR#/DOCR# Note: x indicates a numeric index for the relevant symbol. Figure 9-20.
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32581C Electrical Specifications 9.3.7 LPC Interface Table 9-22. LPC and SERIRQ Timing Parameters Symbol Parameter Min Max Unit tVAL Output Valid delay 0 17 ns After PCICLK rising edge tON Float to Active delay 2 ns After PCICLK rising edge tOFF Active to Float delay ns After PCICLK rising edge tSU Input Setup time 7 ns Before PCICLK rising edge tHI Input Hold time 0 ns After PCICLK rising edge 28 Comments PCICLK tVAL tON LPC Signals/ SERIRQ tOFF Figure 9-21.
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32581C 9.3.8 Electrical Specifications IDE Interface Table 9-23. IDE General Timing Parameters Symbol Parameter Min tIDE_FALL IDE signals fall time (from 0.9VIO to 0.1VIO) tIDE_RISE tIDE_RST_PW Max Unit Comments 5 ns CL = 40 pF IDE signals rise time (from 0.1VIO to 0.9VIO) 5 ns CL = 40 pF IDE_RST# pulse width 25 µs tIDE_RST_PW IDE_RST# Figure 9-23.
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32581C Electrical Specifications Table 9-24.
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32581C Electrical Specifications t0 ADDR valid1 t1 t9 t2 t2i IDE_IOR0# IDE_IOW0# WRITE IDE_DATA[7:0] t3 t4 READ IDE_DATA[7:0] t5 t6 IDE_IORDY02,3 t6z tA IDE_IORDY02,4 tC tRD IDE_IORDY02,5 tB tC Notes: 1) Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0]. 2) Negation of IDE_IORDY0,1 is used to extend the PIO cycle. The determination of whether or not the cycle is to be extended is made by the host after tA from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#.
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32581C Electrical Specifications Table 9-25.
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32581C Electrical Specifications t0 ADDR valid1 t1 t9 t2 t2i IDE_IOR0# IDE_IOW0# WRITE IDE_DATA[15:0] t3 t4 READ IDE_DATA[15:0] t5 t6 IDE_IORDY02,3 t6z tA IDE_IORDY02,4 tC tRD IDE_IORDY02,5 tB tC Notes: 1) Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0]. 2) Negation of IDE_IORDY[0:1] is used to extend the PIO cycle. The determination of whether or not the cycle is to be extended is made by the host after tA from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#.
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32581C Electrical Specifications Table 9-26.
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32581C Electrical Specifications IDE_CS[1:0]# tM tN t0 IDE_DREQ0 tL IDE_DACK0# tI tD tj tK IDE_IOR0# IDE_IOW0# tE tZ IDE_DATA[15:0] tG tF IDE_DATA[15:0] tG tH Notes: 1) For Multiword DMA transfers, the Device may negate IDE_DREQ[0:1] within the tL specified time once IDE_DACK[0:1 is asserted, and reassert it again at a later time to resume the DMA operation.
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32581C Electrical Specifications Table 9-27.
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32581C Electrical Specifications All timing parameters are measured at the connector of the device to which the parameter applies. For example, the sender stops generating STROBE edges tRFS after the IDE_REQ0 (device) negation of DMARDY. Both STROBE and DMARDY timing measurements are taken at the connector of the sender.
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32581C Electrical Specifications t2CYC tCYC tCYC t2CYC IDE_IRDY0 (DSTROBE0) at device tDVS tDVS tDVH tDVH tDVH IDE_DATA[15:0] at device IDE_IRDY0 (DSTROBE0) at host tDH tDS tDH tDS tDH IDE_DATA[15:0] at host Note: IDE_DATA[15:0] and IDE_IRDY[0:1] (DSTROBE[0:1]) signals are shown at both the host and the device to emphasize that cable settling time and cable propagation delay do not allow the data signals to be considered stable at the host until a certain amount of time after they are drive
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32581C Electrical Specifications IDE_DREQ0 (device) IDE_DACK0 (host) tRP IDE_IOW0(STOP0) (host) tSR IDE_IOR0(HDMARDY0) (host) tRFS IDE_IRDY0 (DSTROBE0) (device) IDE_DATA[15:0] (device) Notes: 1) The host can assert IDE_IOW[0:1]# (STOP[0:1]#) to request termination of the UltraDMA burst no sooner than tRP after IDE_IOR[0:1]# (HDMARDY[0:1]#) is de-asserted. 2) If the tSR timing is not satisfied, the host may receive up to two additional data WORDs from the device. Figure 9-29.
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32581C Electrical Specifications IDE_DREQ0 (device) tMLI IDE_DACK0# (host) tLI IDE_IOW0# (STOP0#) (host) tACK tLI tACK tLI IDE_IOR0# (HDMARDY0#) (host) tSS tIORDZ IDE_IRDY0 (DSTROBE0) (device) tZAH tDVS tDVH tAZ IDE_DATA[15:0] (device) CR tACK IDE_CS[0:1]# IDE_ADDR[2:0] Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted.
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32581C Electrical Specifications IDE_DREQ0 (device) tLI IDE_DACK0# (host) tRP tAZ tMLI tACK tZAH IDE_IOW0# (STOP0#) (host) tACK IDE_IOR0# (HDMARDY0#) (host) tRFS tLI tMLI tIORDYZ IDE_IRDY0 (DSTROBE0) (device) tDVS IDE_DATA[15:0] (device) tDVH CR tACK IDE_CS[0:1]# IDE_ADDR[2:0] Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1] (DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1] are de-asserted.
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32581C Electrical Specifications IDE_DREQ0 (device) tUI IDE_DACK0# (host) tACK tENV IDE_IOW0# (STOP0#) (host) tZIORDY IDE_IORDY0 (DDMARDY0) (device) tLI tUI tACK IDE_IOR0# (HSTROBE0#) (host) tDVS tDVH IDE_DATA[15:0] (device) tACK IDE_ADDR[2:0] IDE_CS[0:1]# Note: The definitions for the IDE_IOW[0:1]]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are not in effect until IDE_DREQ[0:1] and IDE_DACK[0:1]# are asserted. Figure 9-32.
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32581C Electrical Specifications t2CYC tCYC tCYC IDE_IOR0# (HSTROBE0#) at host t2CYC tDVS tDVS tDVH tDVH tDVH IDE_DATA[15:0] at host IDE_IOR0# (HSTROBE0#) at device tDH tDS tDH tDS tDH IDE_DATA[15:0] at device Note: IDE_DATA[15:0] and IDE_IOR[0:1]# (HSTROBE[0:1]#) signals are shown at both the device and the host to emphasize that cable settling time and cable propagation delay do not allow the data signals to be considered stable at the device until a certain amount of time after they are
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32581C Electrical Specifications tRP IDE_DREQ0 (device) IDE_DACK0# (host) IDE_IOW0# (STOP0#) (host) tSR IDE_IORDY0# (DDMARDY0#) (device) tRFS IDE_IOR0# (HSTROBE0#) (host) IDE_DATA[15:0] (host) Notes: 1) The device can de-assert IDE_DREQ[0:1] to request termination of the UltraDMA burst no sooner than tRP after IDE_IORDY[0:1]# (DDMARDY[0:1]#) is de-asserted. 2) If the tSR timing is not satisfied, the device may receive up to two additional datawords from the host. Figure 9-34.
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32581C Electrical Specifications tLI IDE_DREQ0 (device) tMLI IDE_DACK0# (host) IDE_IOW0# (STOP0#) (host) tACK tLI tSS tLI tIORDYZ IDE_IORDY0# (DDMARDY0)# (device) tACK IDE_IOR0# (HSTROBE0#) (host) tDVH tDVS IDE_DATA[15:0] (host) CR tACK IDE_ADDR[2:0] IDE_CS[0:1]# Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0,1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted. Figure 9-35.
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32581C Electrical Specifications IDE_DREQ0 (device) IDE_DACK0 (host) tLI tACK tMLI IDE_IOW0# (STOP0#) (host) tIORDZ tRP IDE_IORDY0# (DDMARDY0#) (device) tRFS tLI tMLI tACK IDE_IOR0# (HSTROBE0#) (host) tDVS IDE_DATA[15:0] (host) tDVH CR tACK IDE_CS[0:1]# IDE_ADDR[2:0] Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]# (HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted.
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32581C 9.3.9 Electrical Specifications Universal Serial Bus (USB) Interface Table 9-28.
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32581C Electrical Specifications Table 9-28. USB Timing Parameters (Continued) Symbol Parameter Min Max Unit Figure Comments tUSB_DJU22 Source differential driver jitter for paired transactions –150 150 ns 9-38 Function (downstream), Note 4 tUSB_SE2 Source EOP width 1.25 1.
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32581C Electrical Specifications Rise Time CL 90% Fall Time 90% Differential Data Lines 10% 10% CL tUSB_R1,2 tUSB_F1,2 Full Speed: 4 to 20 ns at CL = 50 pF Low Speed: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF Figure 9-37. Data Signal Rise and Fall Timing Diagram tUSB_DJ11 tUSB_DJD21 tUSB_DJU21 tperiod_F tperiod_L Crossover Points Differential Data Lines (1.3-2.
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32581C Electrical Specifications tperiod_F tperiod_L Data Crossover Level Differential Data Lines Differential Data to SE0 Skew N*tperiod_F + tUSB_DE1 N*tperiod_L + tUSB_DE2 Source: tUSB_SE1, tUSB_SE2 Receiver: tUSB_RE11, tUSB_RE12 tUSB_RE21, tUSB_RE22 EOP Width Figure 9-39.
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32581C 9.3.10 Electrical Specifications Serial Port (UART) Table 9-29.
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32581C Electrical Specifications 9.3.11 Fast IR Port Table 9-30. Fast IR Port Timing Parameters Symbol Parameter tMPW MIR signal pulse width Min Max Unit Comments tMWN-25 (Note 1) tMWN+25 ns Transmitter ns Receiver 60 MDRT MIR transmitter data rate tolerance ± 0.1% tMJT MIR receiver edge jitter, % of nominal bit duration ± 2.
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32581C 9.3.12 Electrical Specifications Parallel Port Interface Table 9-31. Standard Parallel Port Timing Parameters Symbol Parameter Min Typ Max Unit Comments tPDH Port data hold 500 ns Note 1 tPDS Port data setup 500 ns Note 1 tSW Strobe width 500 ns Note 1 Note 1. Times are system dependent and are therefore not tested. BUSY ACK# tPDH tPDS PD[7:0] tSW STB# Figure 9-43.
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32581C Electrical Specifications Table 9-32. Enhanced Parallel Port Timing Parameters EPP 1.
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32581C Electrical Specifications 9.3.12.1 Extended Capabilities Port (ECP) Table 9-33.
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32581C Electrical Specifications Table 9-34. ECP Reverse Mode Timing Parameters Symbol Parameter Min Max Unit tECDSR Data setup before ACK# active 0 ns tECDHR Data hold after AFD# active 0 ns tECLHR AFD# inactive after ACK# active 75 ns tECHHR ACK# inactive after AFD# inactive 0 35 ms tECHLR AFD# active after ACK# inactive 0 1 s tECLLR ACK# active after AFD# active 0 Comments ns tECDHR PD[7:0] BUSY# tECDSR ACK# tECLLR tECLHR AFD# tECHLR tECHHR Figure 9-46.
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32581C 9.3.13 Electrical Specifications Audio Interface (AC97) Table 9-35. AC Reset Timing Parameters Symbol Parameter Min Typ Max Unit tRST_LOW AC97_RST# active low pulse width 1.0 µs tRST2CLK AC97_RST# inactive to BIT_CLK startup delay 162.8 ns Comments tRST2CLK tRST_LOW AC97_RST# BIT_CLK Figure 9-47. AC97 Reset Timing Diagram Table 9-36.
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32581C Electrical Specifications Table 9-37. AC97 Clocks Parameters Symbol Parameter Min Typ Max Unit FBIT_CLK BIT_CLK frequency tCLK_PD BIT_CLK period tCLK_J BIT_CLK output jitter tCLK_H BIT_CLK high pulse width 32.56 tCLK_L BIT_CLK low pulse width 32.56 FSYNC SYNC frequency 48.0 KHz tSYNC_PD SYNC period 20.8 µs tSYNC_H SYNC high pulse width 1.3 µs tSYNC_L SYNC low pulse width 19.5 µs FAC97_CLK AC97_CLK frequency 24.576 MHz tAC97_CLK_PD AC97_CLK period 40.
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32581C Electrical Specifications Table 9-38. AC97 I/O Timing Parameters Symbol Parameter Min Typ Max tAC97_S Input setup to falling edge of BIT_CLK 15.0 ns tAC97_H Hold from falling edge of BIT_CLK 10.
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32581C Electrical Specifications Table 9-39.
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32581C Electrical Specifications Table 9-40. AC97 Low Power Mode Timing Parameters Symbol Parameter Min ts2_pdown End of Slot 2 to BIT_CLK, SDATA_IN low SYNC Slot 1 Typ Max Unit 1.0 µs Comments Slot 2 BIT_CLK SDATA_OUT ts2_pdown SDATA_IN Note: BIT_CLK is not to scale Figure 9-52.
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32581C Electrical Specifications 9.3.14 Power Management Interface LED# Cycle time: 1 s ± 0.1 s, 40%-60% duty cycle. Table 9-41. PWRBTN# Timing Parameters Symbol Parameter Min tPBTNP PWRBTN# pulse width 16 tPBTNE Delay from PWRBTN# events to ONCTL# 14 Max 16 Unit Comments ms Note 1 ms Note 1. Not 100% tested. tPBTNP PWRBTN# tPBTNP tPBTNE tPBTNE ONCTL# Figure 9-53. PWRBTN# Trigger and ONCTL# Timing Diagram Table 9-42.
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32581C 9.3.15 Electrical Specifications Power-Up Sequencing Table 9-43. Power-Up Sequence Using the Power Button Timing Parameters Symbol Parameter Min Max Unit t1 Voltage sequence -100 100 ms Optimum power-up results with t1 = 0. t2 PWRBTN# inactive after VSB or VSBL applied, whichever is applied last 0 1 µs PWRBTN# is an input and must be powered by VSB. t3 PWRBTN# active pulse width 16 4000 ms If PWRBTN# max is exceeded, ONCTL# will go inactive.
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32581C Electrical Specifications Table 9-44. Power-Up Sequence Not Using the Power Button Timing Parameters Symbol Parameter Min Max Unit t1 Voltage sequence -100 100 ms Optimum power-up results with t1 = 0. t2 POR# inactive after VSBL, VCORE, VSB, and VIO applied ms POR# must not glitch during active time. t3 32KHZ startup time VSBL, VCORE1 VSB, VIO2 50 1 s Comments Time required for 32 KHz oscillator and 14.
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32581C 9.3.16 Electrical Specifications JTAG Interface Table 9-45.
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32581C Electrical Specifications TCK t10 t12 TDI, TMS t6 t8 t7 t9 TDO Output Signals t11 t13 Input Signals Figure 9-58.
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32581C 420 Electrical Specifications AMD Geode™ SC3200 Processor Data Book
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Package Specifications 32581C 10 10.0Package Specifications 10.1 Thermal Characteristics The junction-to-case thermal resistance (θJC) of the packages shown in Table 10-1 can be used to calculate the junction (die) temperature under any given circumstance. Table 10-1. θJC (×C/W) Package Max (°C/W) BGU481 5 A maximum junction temperature is not specified since a maximum case temperature is.
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32581C 10.1.1 Package Specifications Heatsink Considerations Table 10-2 on page 421 shows the maximum allowed thermal resistance of a heatsink for particular operating environments. The calculated values, defined as θCA, represent the required ability of a particular heatsink to transfer heat generated by the SC3200 processor from its case into the air, thereby maintaining the case temperature at or below 85°C.
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32581C Package Specifications 10.2 Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 (481-Terminal Ball Grid Array Cavity Up) package. Figure 10-2.
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32581C Package Specifications Figure 10-3.
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Appendix A: Support Documentation 32581C Appendix ASupport Documentation A.1 Order Information Ordering Part Number (AMD OPN)1 Core Frequency (MHz) Core Voltage (VCORE) Temp. (Degree C) 233 1.8V 0 - 85 SC3200UFH-233 SC3200UFH-233F SC3200UFH-266 SC3200UFH-266F Package2 BGU481 BGU481 Pb-free 266 1.8V 0 - 85 BGU481 BGU481 Pb-free 1. The “F” suffix denotes the Pb-free (lead-free) package. See Section 10.
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32581C A.2 Appendix A: Data Book Revision History Data Book Revision History This document is a report of the revision/creation process of the data book for the AMD Geode™ SC3200 processor. Any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table below. Table A-1. Revision History Revision # (PDF Date) Revisions / Comments 0.1 (August 1999) First draft of data book. (For internal review only) 0.2 (October 1999) Second draft. 0.5 (January 2000) Draft. 0.
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Appendix A: Data Book Revision History 32581C Table A-1. Revision History (Continued) Revision # (PDF Date) C (February 2007) Revisions / Comments Table 9-3 "Operating Conditions" on page 352: Change maximum VCORE and VSBL values from 1.89V to 1.99V.
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