Specifications
AMD Geode™ GeodeROM Functional Specification 27
4
POST 32087C
4.0POST
This section outlines the POST (Power-On Self Test) execution flow for GeodeROM, along with the associated checkpoints
that are sent to I/O Port 80h. POST is executed out of xpress.asm. The basic numbering scheme is as follows:
• Reset - 69h, 71h
• Core functions - Numbered in chronological order, starting at 00h
• User functions - 80h and 81h
• Intermediate checkpoints - Numbered in chronological order, beginning on a 10h boundary
• Failing tests - Numbered with xFh and the system halts
4.1 Post Codes
Post
Code
Sub
Code Function Name Function Description
F0h F0h Reset Vector Output just prior to a jump to startTest.
80h --- startTest/UserPreInit Just after startTest. Beginning of POST proper. User-added code to be run
first.
00h startTest/preSioInit Contains board-specific code to initialize SuperI/O (SIO).
60h preSioInit Entering SIO code.
61h preSioInit
6Bh preSioInit Invalid SIO response - try again.
01h --- startTest/clockInit Chipset level clock initialize.
24h clockInit After preparing the memory mapped configuration base of the system clock
control registers.
25h clockInit After setting up UNREAL mode (ES and FS set to 4 GB flat selectors).
26h clockInit After checking if the clock is already setup (getting this code indicates the
clock was not already setup).
27h clockInit After inhibiting writes to CX5520_CLK_CTRL0 and loading values from
CX5520_SCLK and CS5520_SCLK_CTRL0.
28h clockInit Before entering the clock programming loop.
30h clockInit End of one iteration through the clock programming loop.
37h clockInit Reset pressed; entering infinite loop.
E1h clockInit Entering clockInit; see if block is already configured.
E2h clockInit Put configuration block on new address.
E3h clockInit Start Timer 1 and exit.