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AMD Geode™ LX Processors Data Book

AMD Geode™ LX Processors

Data Book

February 2009

Publication ID: 33234H

Summary of content (680 pages)

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AMD Geode™ LX Processors Data Book February 2009 Publication ID: 33234H AMD Geode™ LX Processors Data Book
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© 2009 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice.
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Contents 33234H Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 1.2 2.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . .
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33234H 6.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 7.0 Electrical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 Operating Conditions . . . . . . . .
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List of Figures 33234H List of Figures Figure 1-1. Figure 3-1. Figure 3-2. Figure 4-1. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. Figure 6-10. Figure 6-11. Figure 6-12. Figure 6-13. Figure 6-14. Figure 6-15. Figure 6-16. Figure 6-17. Figure 6-18. Figure 6-19. Figure 6-20. Figure 6-21. Figure 6-22. Figure 6-23. Figure 6-24. Figure 6-25. Figure 6-26. Figure 6-27. Figure 6-28. Figure 6-29. Figure 6-30. Figure 6-31. Figure 6-32. Figure 6-33.
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33234H Figure 6-42. Figure 6-43. Figure 6-44. Figure 6-45. Figure 6-46. Figure 6-47. Figure 6-48. Figure 6-49. Figure 6-50. Figure 6-51. Figure 6-52. Figure 6-53. Figure 6-54. Figure 6-55. Figure 6-56. Figure 6-57. Figure 6-58. Figure 6-59. Figure 6-60. Figure 6-61. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 7-5. Figure 7-6. Figure 7-7. Figure 7-8. Figure 7-9. Figure 9-1. Figure 9-2. Figure A-1. 6 List of Figures Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables 33234H List of Tables Table 2-1. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 5-11. Table 5-12. Table 5-13. Table 5-14. Table 5-15. Table 5-16. Table 5-17. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7.
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33234H Table 6-11. Table 6-12. Table 6-13. Table 6-14. Table 6-15. Table 6-16. Table 6-17. Table 6-18. Table 6-19. Table 6-20. Table 6-21. Table 6-22. Table 6-23. Table 6-24. Table 6-25. Table 6-26. Table 6-27. Table 6-28. Table 6-29. Table 6-30. Table 6-31. Table 6-32. Table 6-33. Table 6-34. Table 6-35. Table 6-36. Table 6-37. Table 6-38. Table 6-39. Table 6-40. Table 6-41. Table 6-42. Table 6-43. Table 6-44. Table 6-45. Table 6-46. Table 6-47. Table 6-48. Table 6-49. Table 6-50. Table 6-51. Table 6-52.
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33234H List of Tables Table 6-66. Table 6-67. Table 6-68. Table 6-69. Table 6-70. Table 6-71. Table 6-72. Table 6-73. Table 6-74. Table 6-75. Table 6-76. Table 6-77. Table 6-78. Table 6-79. Table 6-80. Table 6-81. Table 6-82. Table 6-83. Table 6-84. Table 6-85. Table 6-86. Table 6-87. Table 6-88. Table 6-89. Table 6-90. Table 6-91. Table 6-92. Table 6-93. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Table 7-8. Table 7-9. Table 7-10. Table 7-11. Table 7-12. Table 7-13.
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33234H Table 8-12. Table 8-13. Table 8-14. Table 8-15. Table 8-16. Table 8-17. Table 8-18. Table 8-19. Table 8-20. Table 8-21. Table 8-22. Table 8-23. Table 8-24. Table 8-25. Table 8-26. Table 8-27. Table 8-28. Table 8-29. Table 8-30. Table A-1. Table A-2. Table A-3. 10 List of Tables sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 ss Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Overview 33234H 1 1.0Overview 1.1 General Description AMD Geode™ LX processors are integrated x86 processors specifically designed to power embedded devices for entertainment, education, and business. Serving the needs of consumers and business professionals alike, it’s an excellent solution for embedded applications, such as thin clients, interactive set-top boxes, single board computers, and mobile computing devices. Available with a core voltage of 1.2V, 1.25V, or 1.
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33234H 1.2 Features General Features ■ Functional blocks include: — — — — — — — CPU Core GeodeLink™ Control Processor GeodeLink Interface Units GeodeLink Memory Controller Graphics Processor Display Controller Video Processor – TFT Controller/Video Output Port — Video Input Port — GeodeLink PCI Bridge — Security Block ■ 0.
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33234H Overview Display Controller GeodeLink™ PCI Bridge ■ Hardware frame buffer compression improves Unified ■ PCI 2.2 compliant Memory Architecture (UMA) memory efficiency ■ CRT resolutions supported: — Supports up to 1920x1440x32 bpp at 85 Hz — Supports up to 1600x1200x32 bpp at 100 Hz ■ Supports up to 1600x1200x32 bpp at 60 Hz for TFT ■ Standard Definition (SD) resolution for Video Output Port (VOP): — 720x482 at 59.
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33234H 14 Overview AMD Geode™ LX Processors Data Book
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Architecture Overview 33234H 2 2.0Architecture Overview The CPU Core provides maximum compatibility with the vast amount of Internet content available while the intelligent integration of several other functions, including graphics, makes the AMD Geode™ LX processor a true systemlevel multimedia solution.
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33234H 2.1.2 Memory Management Unit The memory management unit (MMU) translates the linear address supplied by the integer unit into a physical address to be used by the cache unit and the internal bus interface unit. Memory management procedures are x86-compatible, adhering to standard paging mechanisms. The MMU also contains a load/store unit that is responsible for scheduling cache and external memory accesses.
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33234H Architecture Overview 2.5 Graphics Processor • Hardware accelerated rotation BLTs The Graphics Processor is based on the graphics processor used in the AMD Geode GX processor with several features added to enhance performance and functionality.
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33234H 2.6 Display Controller The Display Controller performs the following functions: 1) Retrieves graphics, video, and cursor data. 2) Serializes the streams. 3) Performs any necessary color lookups and output formatting. 4) Interfaces to the Video Processor for driving the display device(s). The Display Controller consists of a memory retrieval system for rasterized graphics data, a VGA, and a back-end filter.
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Architecture Overview 2.10 Security Block The AMD Geode LX processor has an on-chip AES 128-bit crypto acceleration block capable of 44 Mbps throughput on either encryption or decryption at a processor speed of 500 MHz. The AES block runs asynchronously to the processor core and is DMA based. The AES block supports both EBC and CBC modes and has an interface for accessing the optional EEPROM memory for storing unique IDs and/or security keys.
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33234H 20 Architecture Overview AMD Geode™ LX Processors Data Book
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Signal Definitions 33234H 3 3.0Signal Definitions This chapter defines the signals and describes the external interface of the AMD Geode™ LX processor. Figure 3-1 shows the pins organized by their functional groupings. Where signals are multiplexed, the default signal name is listed first and is separated by a plus sign (+). Multi-function pins are described in Table 3-1 on page 22.
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33234H Signal Definitions Table 3-1.
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33234H Signal Definitions 3.1 Buffer Types The Ball Assignment tables starting on page 26 include a column labeled “Buffer Type”. The details of each buffer type listed in this column are given in Table 3-2. The column headings in Table 3-2 are identified as follows: TS: Indicates whether the buffer may be put into the TRISTATE mode.
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33234H 3.2 Bootstrap Options Signal Definitions 3.3 Ball Assignments The bootstrap options shown in Table 3-3 are supported in the AMD Geode LX processor for configuring the system. The tables in this chapter use several common abbreviations. Table 3-4 lists the mnemonics and their meanings. Table 3-3. Bootstrap Options Table 3-4.
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33234H Signal Definitions A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL 1 2 3 4 5 VSS VMEM VSS DQ21 VSS VMEM VSS VSS DQ17 VMEM DQ18 DQ23 VMEM DQ24 DQM3 VMEM DQ27 TLA1 VSS VSS VMEM DQ20 DQ16 VSS VSS VSS 6 7 DQM2 DQ22 8 VSS 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DQ28 DQS3 VSS MA12 DQS2 VMEM DQ19 DQ29 DQ25 DQ30 VMEM MA11 MA9 VSS MA7 MA8 VSS MA5 DQ26 DQ31 VMEM DQ32 VSS VSS DQ37 VMEM DQM4 DQ39 TLA0 DQ36 DQ33 MA0 MA1 V
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33234H Signal Definitions Table 3-5. Ball Assignments - Sorted by Ball Number Ball No. Signal Name (Note 1) Type (PD) Buffer Type Ball No. Signal Name (Note 1) Type (PD) Buffer Type Ball No.
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33234H Signal Definitions Table 3-5. Ball Assignments - Sorted by Ball Number (Continued) Ball No. Signal Name (Note 1) Type (PD) Buffer Type Ball No. Signal Name (Note 1) H2 VSS H3 DQS1 GND --- N28 I/O DDR N29 Type (PD) Buffer Type Ball No.
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33234H Signal Definitions Table 3-5. Ball Assignments - Sorted by Ball Number (Continued) Ball No. Signal Name (Note 1) Type (PD) Buffer Type Ball No.
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33234H Signal Definitions Table 3-5. Ball Assignments - Sorted by Ball Number (Continued) Ball No. Signal Name (Note 1) AK4 DRGB14 VOP9 AK5 VSS AK6 DRGB1 VOP6 AK7 DRGB4 VOP3 AK8 AK9 VSS DRGB31 VID15 AK10 DRGB26 VID10 Type (PD) Buffer Type O (PD) 24/Q5 O Ball No.
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33234H Signal Definitions Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name Signal Name Ball No. Signal Name Ball No. Signal Name Ball No.
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33234H Signal Definitions Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. Signal Name Ball No. Signal Name Ball No.
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33234H Signal Definitions Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name (Continued) Ball No. Signal Name Ball No.
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234H Signal Definitions 3.4 Signal Descriptions 3.4.1 System Interface Signals Signal Name Ball No. Type f V SYSREF Y31 I 33, 66 MHz 3.3 System Reference. PCI input clock; typically 33 or 66 MHz. DOTREF AB1 I 48 MHz 3.3 Dot Clock Reference. Input clock for DOTCLK PLL. INTA# AD28 I/O (PD) 0-66 Mb/s 3.3 Interrupt. Interrupt from the AMD Geode LX processor to the CS5536 companion device (open drain). IRQ13 AB29 (Strap) I/O (PD) 0-66 Mb/s 3.3 Interrupt Request Level 13.
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33234H 3.4.1 Signal Definitions System Interface Signals (Continued) Signal Name Ball No. Type f V TDP AL17 A Analog N/A Description Thermal Diode Positive (TDP). TDP is the positive terminal of the thermal diode on the die. The diode is used to do thermal characterization of the device in a system. This signal works in conjunction with TDN. For accurate die temperature measurements, a dual current source remote sensor, such as the National Semiconductor LM82, should be used.
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33234H Signal Definitions 3.4.3 Memory Interface Signals (DDR) Signal Name Ball No. Type f V Description SDCLK[5:0]P, SDCLK[5:0]N D20, D21, D23, D24, J28, H28, M28, L28, J4, H4, M4, L4 O up to 200 MHz 2.5 SDRAM Clock Differential Pairs. The SDRAM devices sample all the control, address, and data based on these clocks. All clocks are differential clock outputs. MVREF P1 I Analog VMEM Memory Voltage Reference. This input operates at half the VMEM voltage.
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33234H 3.4.3 Signal Definitions Memory Interface Signals (DDR) (Continued) Signal Name DQM[7:0] Ball No. Type f V N30, H29, C24, A19, B10, A6, G2, M1 I/O 166-400 Mb/s 2.5 Description Data Mask Control Bits. During memory read cycles, these outputs control whether the SDRAM output buffers are driven on the Memory Data Bus or not. All DQM signals are asserted during read cycles. During memory write cycles, these outputs control whether or not memory data is written into the SDRAM.
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33234H Signal Definitions 3.4.5 PCI Interface Signals Signal Name AD[31:0] CBE[3:0]# Ball No. Type f V Description See Table 3-6 on page 30 I/O 33-66 Mb/s 3.3 Multiplexed Address and Data. Addresses and data are multiplexed together on the same pins. A bus transaction consists of an address phase in the cycle in which FRAME# is asserted followed by one or more data phases. During the address phase, AD[31:0] contain a physical 32bit address.
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33234H 3.4.5 Signal Definitions PCI Interface Signals (Continued) Signal Name RESET# Ball No. Type f V Y30 I 0-1 Mb/s 3.3 Description PCI Reset. RESET# aborts all operations in progress and places the AMD Geode LX processor into a reset state. RESET# forces the CPU and peripheral functions to begin executing at a known state. All data in the on-chip cache is invalidated upon a reset.
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33234H Signal Definitions 3.4.5 PCI Interface Signals (Continued) Signal Name Ball No. Type f V Description DEVSEL# AK25 I/O 33-66 Mb/s 3.3 Device Select. DEVSEL# indicates that the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. DEVSEL# is also driven by any agent that has the ability to accept cycles on a subtractive decode basis.
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33234H 3.4.6 Signal Definitions TFT Display Interface Signals Signal Name Ball No. Type f V DRGB[31:24] See Table 3-6 on page 30 I/O 0-162 Mb/s 3.3 Display Data Bus. Dot Clock. Output clock from DOTCLK PLL. DRGB[23:0] Description O (PD) DOTCLK AE1 O (PD) 0-162 MHz 3.3 HSYNC AE3 O (PD) 0-162 Mb/s 3.3 (5vt) Horizontal Sync. Horizontal Sync establishes the line rate and horizontal retrace interval for an attached flat panel. The polarity is programmable (See Section 6.8.3.
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33234H Signal Definitions 3.4.7 CRT Display Interface Signals Signal Name Ball No. Type f V HSYNC AE3 I/O 0-350 Mb/s 3.3 (5vt) Horizontal Sync. Horizontal Sync establishes the line rate and horizontal retrace interval for an attached CRT. The polarity is programmable (See Section 6.8.3.2 on page 422, VP Memory Offset 008h[8]). VSYNC AD3 I/O 0-350 Mb/s 3.3 (5vt) Vertical Sync. Vertical Sync establishes the screen refresh rate and vertical retrace interval for an attached CRT.
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33234H 3.4.9 Signal Definitions Power and Ground Interface Signals Signal Name (Note 1) Ball No. Type f V Description VCORE See Table 3-6 on page 30 PWR N/A 1.2 Core Power Connection (Total of 32). VIO See Table 3-6 on page 30 PWR N/A 3.3 I/O Power Connection (Total of 30) VMEM See Table 3-6 on page 30 PWR N/A 2.5 Memory Power Connection (Total of 33). VSS See Table 3-6 on page 30 GND N/A 0 Ground Connection (Total of 128). Note 1.
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33234H Signal Definitions Table 3-7. Signal Behavior During and After Reset Signal Name Type Behavior Signal Name Type Behavior AD[31:0] PCI TRI-STATE during RESET# low VID[7:0] (PD) Video Inputs during RESET# low INTA# PAR VIPCLK CIS System IRDY# TDBGI Debug FRAME# TMS GNT# TDI DEVSEL# TCLK TRDY# SYREF STOP# DOTREF REQ# BA[1:0] System Power-up states after RESET# DDR DRGB[31:24] CAS[1:0]# Video — Display filter can enable outputs to drive alpha (disables PDs).
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33234H 44 Signal Definitions AMD Geode™ LX Processors Data Book
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GeodeLink™ Interface Unit 33234H 4 4.0GeodeLink™ Interface Unit Many traditional architectures use buses to connect modules together, which usually requires unique addressing for each register in every module. This requires that some kind of house-keeping be done as new modules are designed and new devices are created from the module set. Using module select signals to create the unique addresses can get cumbersome and requires that the module selects be sourced from some centralized location.
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33234H 4.1.1 GeodeLink™ Interface Unit Port Address Each GLIU has seven channels with Channel 0 being the GLIU itself and therefore not considered a physical port. Figure 4-1 illustrates the GeodeLink architecture in a AMD Geode LX processor, showing how the modules are connected to the two GLIUs. GLIU0 has five channels connected, and GLIU1 has six channels connected. To get MSR address/data across the PCI bus, the GLPCI converts the MSR address into PCI cycles and back again.
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33234H GeodeLink™ Interface Unit 4.1.2 Port Addressing Exceptions Table 4-2. MSR Mapping There are some exceptions to the port addressing rules. If a module accesses an MSR from within its closest GLIU (e.g., CPU Core accessing a GLIU0 MSR), then, by convention, the port address should be 0.0.0.0.0.0. But this port address accesses an MSR within the source module and not the GLIU as desired.
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33234H Each memory request is compared against all the P2D descriptors. If the memory request does not hit in any of the descriptors, the request is sent to the subtractive port. If the memory requests hit more than one descriptor, the results are undefined. The software must provide a consistent non-overlapping address map. The way each descriptor checks if the request address hits its descriptor and how to route the request address to the device address is described in Table 4-3.
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33234H GeodeLink™ Interface Unit 4.1.3.2 I/O Routing and Translation I/O addresses are routed and are never translated. I/O request routing is performed with a choice of two descriptor types. Each GLIU may have any number of each descriptor type. The IOD types satisfy different needs for various software models. Each I/O request is compared against all the IOD. If the I/O request does not hit in any of the descriptors, the request is sent to the subtractive port.
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33234H 4.2 GLIU Register Descriptions GLIU Register Descriptions All GeodeLink™ Interface Unit (GLIU) registers are Model Specific Registers (MSRs) and are accessed through the RDMSR and WRMSR instructions. The registers associated with the GLIU are the Standard GeodeLink Device (GLD) MSRs, GLIU Specific MSRs. GLIU Statistic and Comparator MSRs, P2D Descriptor MSRs, and I/O Descriptor MSRs.
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33234H GLIU Register Descriptions Table 4-6.
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33234H GLIU Register Descriptions Table 4-7.
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33234H GLIU Register Descriptions Table 4-7. GLIU Statistic and Comparator MSRs Summary (Continued) MSR Address Type Register Reset Value Reference GLIU0: 100000DEh GLIU1: 400000DEh R/W Data Compare Mask Low (DA_COMPARE_MASK_LO[3]) 00000000_00000000h Page 78 GLIU0: 100000DFh GLIU1: 400000DFh R/W Data Compare Mask High (DA_COMPARE_MASK_HI[3]) 00000000_00000000h Page 79 Table 4-8.
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33234H GLIU Register Descriptions Table 4-10.
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33234H GLIU Register Descriptions 4.2.1 Standard GeodeLink™ Device (GLD) MSRs 4.2.1.
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33234H GLIU Register Descriptions 4.2.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address GLIU0: 10002002h GLIU1: 40002002h Type R/W Reset Value 00000000_00000001h The flags are set with internal conditions. The internal conditions are always capable of setting the flag, but if the mask is 1, the flagged condition will not trigger the SMI signal. Reads to the flags return the value. Write = 1 to the flag, clears the value. Write = 0 has no effect on the flag.
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33234H GLIU Register Descriptions 4.2.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address GLIU0: 10002003h GLIU1: 40002003h Type R/W Reset Value 00000000_00000000h The flags are set with internal conditions. The internal conditions are always capable of setting the flag, but if the mask is 1, the flagged condition will not trigger the ERR signal. Reads to the flags return the value. Write = 1 to the flag, clears the value. Write = 0 has no effect on the flag.
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33234H GLIU Register Descriptions GLD_MSR_ERROR Bit Descriptions (Continued) Bit Name Description 39 EFLAG7 Request Comparator Error Flag 0. If high, records that an ERR was generated due to a Request Comparator 0 (RQ_COMPARE_VAL0, GLIU0 MSR 100000C0h, GLIU1 MSR 400000C0h) event. Write 1 to clear; writing 0 has no effect. EMASK7 (bit 7) must be low to generate ERR and set flag. 38 EFLAG6 Statistic Counter Error Flag 3.
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33234H GLIU Register Descriptions GLD_MSR_ERROR Bit Descriptions (Continued) Bit Name Description 8 EMASK8 Request Comparator Error Mask 1. Write 0 to enable EFLAG8 (bit 40) and to allow a Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR 400000C2h) event to generate an ERR 7 EMASK7 Request Comparator Error Mask 0.
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33234H GLIU Register Descriptions GLD_MSR_PM Bit Descriptions Bit Name Description 63:4 RSVD Reserved. 3:2 PMODE_1 Power Mode 1. Statistics and Time Slice Counters. 00: Disable clock gating. Clocks are always on. 01: Enable hardware clock gating. Clock goes off whenever this module’s circuits are not busy. 10, 11: Reserved. 1:0 PMODE_0 Power Mode 0. Online GLIU logic. 00: Disable clock gating. Clocks are always on. 01: Enable hardware clock gating.
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33234H GLIU Register Descriptions 4.2.2.2 Port Active Enable (PAE) MSR Address GLIU0: 10000081h GLIU1: 40000081h Type R/W Reset Value Boot Strap Dependent Ports that are not implemented return 00 (RSVD). Ports that are slave only return 11. Master/Slave ports return the values as stated. GLIU0 will reset all PAE to 11 (ON) except that GLIU0 PAE3 resets to 00 when the debug stall bootstrap is active (CPU port resets inactive for debug stall).
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33234H GLIU Register Descriptions 4.2.2.3 Arbitration (ARB) MSR Address GLIU0: 10000082h GLIU1: 40000082h Type R/W Reset Value 10000000_00000000h ARB Register Map RSVD DACK_EN RSVD PIPE_DIS QUACK_EN 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD ARB Bit Descriptions Bit Name Description 63 QUACK_EN Quadruple Acknowledge Enabled.
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33234H GLIU Register Descriptions ASMI Bit Descriptions Bit Name Description 63:16 RSVD Reserved. 15 ASMI_MASK7 Asynchronous SMI Mask for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.) Write 0 to allow Port 7 to generate an ASMI. ASMI status is reported in bit 7. 14 ASMI_MASK6 Asynchronous SMI Mask for Port 6. (GLIU0 = Not Used; GLIU1 = SB.) Write 0 to allow Port 6 to generate an ASMI. ASMI status is reported in bit 6. 13 ASMI_MASK5 Asynchronous SMI Mask for Port 5. (GLIU0 = GP; GLIU1 = VIP.
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33234H GLIU Register Descriptions AERR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 9 8 7 6 5 4 3 2 1 0 AERR_MASK0 AERR7 AERR6 AERR5 AERR4 AERR3 AERR2 AERR1 AERR0 AERR_MASK2 AERR_MASK3 AERR_MASK4 AERR_MASK5 AERR_MASK6 RSVD AERR_MASK7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AERR_MASK1 RSVD AERR Bit Descriptions 64 Bit Name Description 63:16 RSVD Reserved.
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33234H GLIU Register Descriptions 4.2.2.
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33234H GLIU Register Descriptions 4.2.2.
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33234H GLIU Register Descriptions 4.2.2.
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33234H GLIU Register Descriptions SLAVE_ONLY Bit Descriptions (Continued) Bit Name Description 6 P6_SLAVE_ONLY Port 6 Slave Only. (GLIU0 = Not Used; GLIU1 = SB.) If high, indicates that Port 6 is a slave port. If low, Port 6 is a master/slave port. 5 P5_SLAVE_ONLY Port 5 Slave Only. (GLIU0 = GP; GLIU1 = VIP.) If high, indicates that Port 5 is a slave port. If low, Port 5 is a master/slave port. 4 P4_SLAVE_ONLY Port 4 Slave Only. (GLIU0 = DC; GLIU1 = GLPCI.
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33234H GLIU Register Descriptions 4.2.2.11 GLIU Slave Disable (GLIU_SLV) MSR Address GLIU0: 1000008Ch GLIU1: 4000008Ch Type R/W Reset Value 00000000_00000000h The slave disable registers are available for the number of ports on the GLIU. The unused ports return 0.
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33234H GLIU Register Descriptions 4.2.2.12 Arbitration2 (ARB2) MSR Address GLIU0: 1000008Dh GLIU1: 4000008Dh Type R/W Reset Value 00000000_00000000h ARB2 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 THROT_EN RSVD 1 0 THRESH ARB2 Bit Descriptions Bit Name Description 63:4 RSVD Reserved. THROT_EN Arbitration Throttling Enable.
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33234H GLIU Register Descriptions 4.2.3 GLIU Statistic and Comparator MSRs 4.2.3.
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33234H 4.2.3.
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33234H GLIU Register Descriptions 4.2.3.
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33234H GLIU Register Descriptions STATISTIC_ACTION[0:3] Bit Descriptions Bit 2 Name Description HIT_ASMI Assert ASMI on Descriptor Hit. The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 1 HIT_DEC Decrement Counter on Descriptor Hit. The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 0 HIT_LDEN Load Counter on Descriptor Hit. The descriptor hits are ANDed with the masks and then all ORed together.
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33234H GLIU Register Descriptions 4.2.3.5 Request Compare Mask (RQ_COMPARE_MASK[0:3] The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger the RQ_CMP error sources when they are enabled. The value is compared only after the packet is arbitrated.
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33234H GLIU Register Descriptions 4.2.3.6 DA Compare Value Low (DA_COMPARE_VAL_LO[0:3] The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is determined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). A hit can trigger the DA_CMP error sources when they are enabled. The value is compared only after the packet is arbitrated.
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33234H GLIU Register Descriptions 4.2.3.7 DA Compare Value High (DA_COMPARE_VAL_HI[0:3] The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is determined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). A hit can trigger the DA_CMP error sources when they are enabled. The value is compared only after the packet is arbitrated.
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33234H 4.2.3.
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33234H GLIU Register Descriptions 4.2.3.
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33234H 4.2.4 GLIU Register Descriptions P2D Descriptor Registers P2D descriptors are ordered P2D_BM, P2D_BMO, P2D_R, P2D_RO, P2D_SC, P2D_BMK. For example if NP2D_BM=3 and NP2D_BM0=2, IMSR EO = P2D_BM[0], MSR E3 = P2D_SC[0]. 4.2.4.1 P2D Base Mask Descriptor (P2D_BM) GLIU0 P2D_BM[5:0] MSR Address 10000020h-10000025h Type R/W Reset Value 000000FF_FFF00000h GLIU1 MSR Address Type Reset Value P2D_BM[9:0] 40000020h-40000029h R/W 000000FF_FFF00000h See Table 4.1.3.
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33234H GLIU Register Descriptions 4.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO) GLIU0 P2D_BMO[1:0] MSR Address 10000026h-10000027h Type R/W Reset Value 00000FF0_FFF00000h See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
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33234H GLIU Register Descriptions 4.2.4.3 P2D Range Descriptor (P2D_R) GLIU0 P2D_R[0] MSR Address 10000028h Type R/W Reset Value 00000000_000FFFFFh GLIU1 MSR Address Type Reset Value P2D_R[3:0] 4000002Ah-4000002Dh R/W 00000000_000FFFFFh See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
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33234H GLIU Register Descriptions 4.2.4.4 P2D Range Offset Descriptor (P2D_RO) GLIU0 P2D_RO[2:0] MSR Address 10000029h-1000002Bh Type R/W Reset Value 00000000_000FFFFFh See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
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33234H GLIU Register Descriptions 4.2.4.5 P2D Swiss Cheese Descriptor (P2D_SC) GLIU0 P2D_SC[0] MSR Address 1000002Ch Type R/W Reset Value 00000000_00000000h GLIU1 MSR Address Type Reset Value P2D_SC[0] 4000002Eh R/W 00000000_00000000h See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
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33234H GLIU Register Descriptions 4.2.5 SPARE MSRs (SPARE_MSR[0:9], A:F) MSR Address Type Reset Value GLIU0: 10000040h-1000004Fh GLIU1: 40000040h-4000004Fh R/W 00000000_00000000h SPARE_MSR[x] Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 SPARE_MSR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPARE_MSR SPARE_MSR[x] Bit Descriptions Bit 63:0 Name Description SPARE_MSR Spare MSR.
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33234H 4.2.6 GLIU Register Descriptions I/O Descriptors I/O descriptors are ordered IOD_BM, IOD_SC. For example if NIOD_BM = 3 and NIOD_SC = 2, MSR 100000EOh = IOD_BM[0] and MSR 100000E3h = IOD_SC[0]. 4.2.6.1 IOD Base Mask Descriptors (IOD_BM) GLIU0 IOD_BM[0:3] MSR Address 100000E0h-100000E2h Type R/W Reset Value 000000FF_FFF00000h GLIU1 MSR Address Type Reset Value IOD_BM[0:3] 400000E0h-400000E2h R/W 000000FF_FFF00000h See Table 4.1.3.
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33234H GLIU Register Descriptions 4.2.6.2 IOD Swiss Cheese Descriptors (IOD_SC) GLIU0 IOD_SC[0:5] MSR Address 100000E3h-100000E8h Type R/W Reset Value 00000000_00000000h GLIU1 MSR Address Type Reset Value IOD_SC[0:3] 400000E3h-400000E6h R/W 00000000_00000000h See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
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33234H 88 GLIU Register Descriptions AMD Geode™ LX Processors Data Book
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CPU Core 33234H 5 5.0CPU Core This section describes the internal operations of the AMD Geode™ LX processor’s CPU Core from a programmer’s point of view. It includes a description of the traditional “core” processing and FPU operations. The integrated function registers are described in the next chapter. The primary register sets within the processor core include: • Application Register Set • System Register Set 5.
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33234H 5.2 Instruction Set Overview The CPU Core instruction set can be divided into nine types of operations: • Arithmetic CPU Core The Processor Core Instruction Set (see Table 8-26 on page 634) contains the clock count table that lists each instruction in the CPU instruction set. Included in the table are the associated opcodes, execution clock counts, and effects on the EFLAGS register. • Bit Manipulation • Shift/Rotate 5.2.
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33234H CPU Core 5.3 Application Register Set The Application Register Set consists of the registers most often used by the applications programmer. These registers are generally accessible, although some bits in the EFLAGS registers are protected. The General Purpose register contents are frequently modified by instructions and typically contain arithmetic and logical instruction operands. In real mode, Segment registers contain the base address for each segment.
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33234H 5.3.1 CPU Core General Purpose Registers The General Purpose registers are divided into four data registers, two pointer registers, and two index registers as shown in Table 5-2 on page 91. The Data registers are used by the applications programmer to manipulate data structures and to hold the results of logical and arithmetic operations. Different portions of general data registers can be addressed by using different names. An “E” prefix identifies the complete 32-bit register.
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33234H CPU Core 5.3.4 EFLAGS Register The EFLAGS register contains status information and controls certain operations on the Geode LX processor. The lower 16 bits of this register are used when executing 8086 or 80286 code. Table 5-4 gives the bit formats for the EFLAGS register. Table 5-4. EFLAGS Register Bit Name Flag Type Description 31:22 RSVD -- 21 ID System 20:19 RSVD -- 18 AC System Alignment Check Enable.
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33234H 5.4 CPU Core System Register Set The System Register Set, shown in Table 5-5, consists of registers not generally used by application programmers. These registers are either initialized by the system BIOS or employed by system level programmers who generate operating systems and memory management programs. Associated with the System Register Set are certain tables and registers that are listed in Table 5-5. Table 5-5.
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33234H CPU Core 5.4.1 Control Registers A map of the Control registers (CR0, CR1, CR2, CR3, and CR4) is shown in Table 5-6 and the bit descriptions are in the tables that follow. (These registers should not be confused with the CRRn registers.) CR0 contains system control bits that configure operating modes and indicate the general state of the CPU. The lower 16 bits of CR0 are referred to as the Machine Status Word (MSW).
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33234H CPU Core Table 5-7. CR4 Bit Descriptions Bit Name Description 31:9 RSVD Reserved. Set to 0 (always returns 0 when read). 8 PCE Performance Counter Enable. Set PCE = 1 to make RDPMC available at nonzero privilege levels. 7 PGE Page Global Enable. Set PGE = 1 to make global pages immune to INVLPG instructions. 6:5 RSVD Reserved. Set to 0 (always returns 0 when read). 4 PSE Page Size Extensions. Set PSE = 1 to enable 4 MB pages. 3 DE Debug Extensions.
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33234H CPU Core Table 5-10. CR0 Bit Descriptions (Continued) Bit Name Description 30 CD 29 NW Cache Disable/Not Write-Through (Snoop). Cache behavior is based on the CR0 CD and NW bits. 28:19 CD NW 0 0 Normal Cache operation, coherency maintained. Read hits access the cache, Write hits update the cache, Read/write misses may cause line allocations based on memory region configuration settings. 0 1 Invalid, causes a General Protection Fault (GPF). 1 0 Cache off, coherency maintained (i.
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33234H CPU Core Table 5-11.
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33234H CPU Core Register Descriptions 5.5 CPU Core Register Descriptions All CPU Core registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instructions. Each module inside the processor is assigned a 256 register section of the address space. The module responds to any reads or writes in that range. Unused addresses within a module’s address space are reserved, meaning the module returns zeroes on a read and ignores writes.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H CPU Core Register Descriptions Table 5-13.
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33234H 5.5.1 CPU Core Register Descriptions Standard GeodeLink™ Device MSRs 5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address 00002000h Type RO Reset Value 00000000_000864xxh GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 DEV_ID 4 3 2 1 0 REV_ID GLD_MSR_CAP Bit Descriptions Bit Name Description 63:24 RSVD Reserved.
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CPU Core Register Descriptions 33234H 5.5.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 00002002h Type R/W Reset Value 00000000_00000000h This register is not used in the CPU Core module. 5.5.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 00002003h Type R/W Reset Value 00000000_00000000h This register is not used in the CPU Core module. 5.5.1.5 GLD Power Management MSR (GLD_MSR_PM) MSR Address 00002004h Type R/W Reset Value 00000000_00000000h This register is not used in the CPU Core module. 5.5.1.
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33234H 5.5.2 CPU Core Register Descriptions CPU Core Specific MSRs 5.5.2.1 Time Stamp Counter MSR (TSC_MSR) MSR Address 00000010h Type R/W Reset Value 00000000_00000000h TSC_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 TSC (High DWORD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSC (Low DWORD) TSC_MSR Bit Descriptions Bit 63:0 Name Description TSC Time Stamp Counter.
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33234H CPU Core Register Descriptions 5.5.2.3 Performance Event Counter 1 MSR (PERF_CNT1_MSR) MSR Address 000000C2h Type R/W Reset Value 00000000_00000000h PERF_CNT1_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PERF_CNT1 (High Byte) 9 8 7 6 5 4 3 2 1 0 PERF_CNT1 (Low DWORD) PERF_CNT1_MSR Bit Descriptions Bit Name Description 63:40 RSVD Reserved.
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33234H CPU Core Register Descriptions 5.5.2.4 SYSENTER/SYSEXIT Code Segment Selector MSR (SYS_CS_MSR) MSR Address 00000174h Type R/W Reset Value 00000000_C09B0000h SYS_CS_MSR is used by the SYSENTER instruction (fast system call) as the selector of the most privileged code segment. SYS_CS plus 8 is used by SYSENTER as the selector of the most privileged stack segment. SYS_CS plus 16 is used by SYSEXIT as the selector of the least privileged code segment.
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33234H CPU Core Register Descriptions 5.5.2.5 SYSENTER/SYSEXIT Stack Pointer MSR (SYS_SP_MSR) MSR Address 00000175h Type R/W Reset Value 00000000_00000000h SYS_SP MSR is used by the SYSENTER instruction (fast system call) as the most privileged stack pointer.
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33234H CPU Core Register Descriptions 5.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR MSR Address 00000186h Type R/W Reset Value 00000000_00000000h PERF_SEL0_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD PC_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD RSVD 9 8 7 6 PC0_UMASK 5 4 3 2 1 0 PC0_EVENT PERF_SEL0_MSR Bit Descriptions Bit Name Description 63:23 RSVD Reserved.
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33234H CPU Core Register Descriptions 5.5.2.9 Instruction Fetch Configuration MSR (IF_CONFIG_MSR) MSR Address 00001100h Type R/W Reset Value 00000000_00005051h IF_CONFG_MSR controls the operation of the Instruction Fetch (IF). The Level-0 COF cache (Change of Flow (COF) cache), L1 COF cache, return stack, and power saving mode may be turned on or off. The WRMSR instruction can access IF_CONFIG MSR at any time.
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33234H CPU Core Register Descriptions IF_CONFIG_MSR Bit Descriptions (Continued) Bit Name Description 28 II_NS Instruction Pipeline (IP) Empty Mode. 0: IM Interface may make requests to Instruction Memory (IM) when the IP is not empty. (Default) 1: IM Interface only makes requests to IM after the IP is empty. Note: 27:25 24 Enabling this mode reduces performance. RSVD Reserved. CC_SER COF Cache Serialization. 0: Allow more than one outstanding request in COF cache.
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33234H CPU Core Register Descriptions IF_CONFIG_MSR Bit Descriptions (Continued) Bit 6 Name Description STRONG Strong Prediction. Allow the IF to make strong predictions. 0: Disable. 1: Enable. (Default) Note: Enabling strong predictions may improve performance. 5 RSVD Reserved. 4 RS Return Stack. 0: Disable. 1: Enable. (Default) Note: Enabling the return stack increases performance unless CC_L1 is enabled (bit 0 = 1), then the return stack has no effect. 3 RSVD Reserved.
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33234H CPU Core Register Descriptions 5.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR) MSR Address 00001102h Type W Reset Value 00000000_00000000h IF_INVALIDATE MSR may be used to invalidate the contents of the Tag RAMs (Level-1 COF cache), Level-0 COF cache, and the return stack. Devices external to the CPU should issue writes to IF_INVALIDATE_MSR only if the CPU is suspended or stalled.
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33234H CPU Core Register Descriptions IF_TEST_ADDR_MSR Bit Descriptions (Continued) Bit 12:8 Name Description BLOCK Block Identifier. 00h: 01h: 02h: 03h: 04h: 05h: 06h: 07h: 08h: 09h: 0Ah: 0Bh: 0Ch: 0Dh: 0Eh: 0Fh: 10h: 11h: 12h: 13h: 14h: 15h: 7:0 INDEX Target RAM 0 (Way 0). (Default) Target RAM 1 (Way 0). Target RAM 2 (Way 0). Target RAM 3 (Way 0). Target RAM 4 (Way 1). Target RAM 5 (Way 1). Target RAM 6 (Way 1). Target RAM 7 (Way 1). Target RAM 8 (Way 2). Target RAM 9 (Way 2).
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33234H CPU Core Register Descriptions IF_TEST_DATA_MSR Register Map for Tag RAMs 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 V LIP RSVD STRENGTH 9 8 7 6 5 TYPE 4 3 2 1 0 END IF_TEST_DATA_MSR Bit Descriptions for Tag RAMs Bit Name Description 63:32 RSVD Reserved. V Tag is Valid. (Default = 0) 30:22 LIP Linear Address Bits [19:11]. 21:20 RSVD Reserved.
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33234H CPU Core Register Descriptions IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR[31:0] IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Address Bit Name Description 63:32 RSVD Reserved. 31:0 ADDR[31:0] Address Bits [31:0]. Linear address for which the entry contains data.
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33234H CPU Core Register Descriptions IF_TEST_DATA_MSR Register Map for Return Stack Valids 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD ID_SPEC_VLD 9 8 7 IF_SPEC_VLD[7:0] 6 5 4 3 2 1 0 NONSPEC_VLD[7:0] IF_TEST_DATA_MSR Bit Descriptions for Return Stack Valids Bit Name Description 63:24 RSVD Reserved. 23:16 ID_SPEC_VLD Valid Instruction Decode Speculative.
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33234H CPU Core Register Descriptions 5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR) MSR Address 00001140h Type RO Reset Value 00000000_00000000h IF_BIST_MSR may be used to run built-in self-test (BIST) on the IF Tag and Target RAMs, and to get an indication of whether the BIST run passed or failed. There are separate BIST controllers for the Tag RAM and for the Target RAMs. A MSR read of IF_BIST_MSR causes BIST to be run.
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33234H CPU Core Register Descriptions 5.5.2.15 Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR) MSR Address 00001210h Type R/W Reset Value 00000000_00000000h XC_CONFIG_MSR allows the processor to be configured so that when the processor is in its HALT state, it can request that its clocks be turned off. It also allows the processor to be configured so that the processor is suspended when a PAUSE instruction is executed.
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33234H CPU Core Register Descriptions 5.5.2.16 XC Mode MSR (XC_MODE_MSR) MSR Address 00001211h Type R/W Reset Value 00000000_00000000h XC_MODE_MSR contains information about the current status of the processor.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR) MSR Address 00001213h Type RO Reset Value 00000000_00000000h XC_UADDR_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD UADDR4 UADDR3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 UADDR2[7:0] 9 UADDR2[11:8] 8 7 UADDR1 6 5 4 3 2 1 0 UADDR0 XC_UADDR_MSR Bit Descriptions Bit Name Description 63:60 RSVD Reserved.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions DMI Control Register Bit Descriptions (Continued) Bit 1 Name Description DMI_GPF DMI General Protection Faults. When enabled and not in DMM mode, allow general protection faults to generate DMIs. 0: Disable. 1: Enable. 0 DMI_INST DMI Instructions. Enable DMI instructions DMINT and RDM. If not enabled, executing a DMI instruction generates an invalid operation fault. 0: Disable. 1: Enable. 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.23 Segment Selector/Flags MSRs The Segment Selector/Flags MSRs provide access to the segment selector and segment flags parts of a segment register. The contents of segment registers should be accessed using MOV or SVDC/RSDC.
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33234H CPU Core Register Descriptions Segment Selector/Flags MSR Bit Descriptions (Continued) Bit Name Description 19 X Executable Non-System Segment. 18 E/C Expand Down Data Segment / Conforming Code Segment. 17 W/R Writable Data Segment / Readable Code Segment. 16 A Accessed Segment. SELECTOR Segment Selector. TI Descriptor Table Indicator (LDT/GDT). RPL Requestor Privilege Level. 15:3 2 1:0 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.25 DMM Header MSR (DMM_HDR_MSR) MSR Address 0000132Ch Type R/W Reset Value 00000000_00000000h DMM_HDR_MSR provides access to the address register that controls where DMI data is written.
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33234H CPU Core Register Descriptions 5.5.2.26 Segment Base/Limit MSRs The segment base/limit MSRs provide access to the segment limit and segment base parts of a segment register. The limit value is the true limit; it does not need to be altered based on the limit granularity bit. The contents of segment registers should be accessed using MOV or SVDC/RSDC.
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33234H CPU Core Register Descriptions 5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR) MSR Address 00001340h Type R/W Reset Value xxxxxxxx_xxxxxxxxh DR1_DR0_MSR provides access to Debug Register 1 (DR1) and Debug Register 0 (DR0). DR0 and DR1 each contain either an I/O port number or a linear address for use as a breakpoint. The contents of debug registers are more easily accessed using the MOV instruction.
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33234H CPU Core Register Descriptions 5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR) MSR Address 00001343h Type R/W Reset Value 00000000_FFFF0000h DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status information about debug conditions that have occurred. DR7 contains debug condition enables, types, and lengths. The contents of debug registers are more easily accessed using the MOV instruction.
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33234H CPU Core Register Descriptions 5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR) MSR Address 00001350h Type R/W Reset Value 00000000_00000000h XDR1/XDR0_MSR provides access to Extended Debug Register 1 (XDR1) and Extended Debug Register 0 (XDR0). XDR0 and XDR1 each contain either an I/O port number or a linear address for use as an extended breakpoint.
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33234H CPU Core Register Descriptions 5.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR) MSR Address 00001352h Type R/W Reset Value FFFFFFFF_00000000h XDR5/XDR4_MSR provides access to Extended Debug Register 5 (XDR5) and Extended Debug Register 4 (XDR4). XDR4 contains an opcode match value. XDR5 contains an opcode match mask.
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33234H CPU Core Register Descriptions XDR7_XDR6_MSR Bit Descriptions Bit Name Description 63:62 LEN3 Extended Breakpoint 3 Length. 61:60 TYPE3 Extended Breakpoint 3 Type. 59:58 LEN2 Extended Breakpoint 2 Length. 57:56 TYPE2 Extended Breakpoint 2 Type. 55:54 LEN1 Extended Breakpoint 1 Length. 53:52 TYPE1 Extended Breakpoint 1 Type. 51:50 LEN0 Breakpoint 0 Length. 49:48 TYPE0 Breakpoint 0 Type. 47:39 RSVD Reserved. 38 E6 Extended Breakpoint 6 Enable.
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33234H CPU Core Register Descriptions 5.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR) MSR Address 00001354h Type R/W Reset Value FFFFFFFF_00000000h XDR9_XDR8_MSR provides access to Extended Debug Register 9 (XDR9) and Extended Debug Register 8 (XDR8). XDR8 contains an opcode match value. XDR9 contains an opcode match mask.
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33234H CPU Core Register Descriptions 5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR) MSR Address 00001355h Type R/W Reset Value xxxxxxxx_xxxx0000h XDR11_XDR10_MSR provides access to the extended I/O breakpoint.
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33234H CPU Core Register Descriptions 5.5.2.37 WB Stage Instruction Pointer MSR (WB_IP_MSR) MSR Address 00001361h Type R/W Reset Value 00000000_00000000h WB_IP_MSR provides access to the WB stage instruction pointer (effective address).
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33234H CPU Core Register Descriptions 5.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR) MSR Address 00001365h Type RO Reset Value 00000000_00000000h WB_LIP_MSR provides access to the WB stage linear instruction pointer.
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33234H CPU Core Register Descriptions 5.5.2.41 C3/C2 Linear Instruction Pointer MSR (C3_C2_LIP_MSR) MSR Address 00001367h Type RO Reset Value 00000000_00000000h C3_C2_LIP_MSR provides access to linear instruction pointers when the code segment was loaded.
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33234H CPU Core Register Descriptions 5.5.2.43 Floating Point Environment Instruction Pointer (FPENV_IP_MSR) MSR Address 00001371h Type R/W Reset Value 00000000_00000000h FPENV_IP_MSR provides access to the floating point (FP) environment instruction pointer. Software better accesses the floating point environment data using the FLDENV/FSTENV and FSAVE/FRSTOR instructions.
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33234H CPU Core Register Descriptions 5.5.2.45 Floating Point Environment Data Pointer (FPENV_DP_MSR) MSR Address 00001373h Type R/W Reset Value 00000000_00000000h FPENV_DP_MSR provides access to the floating point (FP) environment data pointer. Software better accesses the floating point environment data using the FLDENV/FSTENV and FSAVE/FRSTOR instructions.
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33234H CPU Core Register Descriptions 5.5.2.47 Address Calculation Unit Configuration MSR (AC_CONFIG_MSR) MSR Address 00001380h Type RO Reset Value 00000000_00000000h AC_CONFIG_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 9 8 7 6 5 4 3 2 RSVD 1 0 LOCK_EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AC_CONFIG_MSR Bit Descriptions Bit Name Description 63:1 RSVD Reserved. LOCK_EN Lock Enable.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions IM_CONFIG_MSR Bit Descriptions (Continued) Bits 8 Name Description ICD Instruction Cache Disable. Completely disable L0 and L1 instruction caches. Contents of cache is not modified and no cache entry is read. 0: Use standard x86 cacheability rules. (Default) 1: Instruction cache will always generate a miss. 7 TUS Translation Look-aside Buffer Updates Select. Select L1 TLB updates (not L1 TLB evictions) to go out on the IM’s Translation Bus.
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33234H CPU Core Register Descriptions 5.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR) MSR Address 00001710h Type R/W Reset Value 00000000_00000000h IC_INDEX_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD DSEL RSVD 9 8 7 6 5 4 WAY 3 2 1 0 LINE IC_INDEX_MSR Bit Descriptions Bits Name Description 63:18 RSVD (RO) Reserved (Read Only).
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33234H CPU Core Register Descriptions 5.5.2.54 Instruction Cache Tag (IC_TAG_MSR) MSR Address 00001712h Type R/W Reset Value 00000000_00000000h IC_TAG_MSR MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD LRU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TAG 8 7 6 5 4 3 2 1 RSVD 0 V IC_TAG_MSR Bit Descriptions Bits Name Description 63:47 RSVD (RO) Reserved (Read Only).
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions L0_IC_TAG_I_MSR Bit Descriptions Bits Name Description 63:32 RSVD Reserved. 31:16 TLB_NUM TLB Number. This is the one-hot-value of the TLB entry corresponding to the L0 cache entry. (Default = 0) 15:12 RSVD Reserved. 11:8 TAG 7:3 LINE Tag/Line. This is a combination of the 4-bit tag and the 5-bit line. Together they make up bits [11:3] of the physical address for the line selected by IC_INDEX_MSR (MSR 00001710h). 2:1 RSVD Reserved. V Valid.
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33234H CPU Core Register Descriptions 5.5.2.59 L1 Instruction TLB Least Recently Used MSR (ITB_LRU_MSR) MSR Address 00001721h Type R/W Reset Value 00000000_00000000h ITB_LRU_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 LRU ITB_LRU_MSR Bit Descriptions Bits Name Description 63:30 RSVD (RO) Reserved (Read Only).
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.61 Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR) MSR Address 00001730h Type RO Reset Value 00000000_0000000xh The Instruction Memory subsystem supports built-in self-test (BIST) for the tag and data arrays. Normally, BIST is run during manufacturing test. For convenience, BIST can be activated by reading the BIST MSRs. WARNING: It is important that the instruction cache be disabled before initiating BIST via MSRs.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions DM_CONFIG0_MSR Bit Descriptions (Continued) Bits Name Description 32 WBDIS Write Buffer Disable. Disabling the write buffer forces stores to be sent directly from the output of the store queue to the bus controller. Enabling the write buffer allows memory stores to be buffered, with or without combining based on region properties. 0: Enable write buffer. (Default) 1: Disable write buffer.
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33234H CPU Core Register Descriptions DM_CONFIG0_MSR Bit Descriptions (Continued) Bits 7 Name Description SPCDEC Decrease Number of Speculative Reads of Data Cache. 0: Actively resync cache tag and data arrays so that loads can be speculatively handled in one clock if the MRU way is hit. (Default) 1: Do not attempt to resync cache tag and data arrays. This is a performance optimization bit and the preferred value may have to be empirically determined.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions DM_CONFIG1_MSR Bit Descriptions (Continued) Bits 20 19:16 Name Description NOPFXEVCT No Prefetch Prefix Evictions. This bit disables clean line eviction in the case where a new allocation occurs on a load/store miss when a move string operation uses the REPNZ prefix instead of the normal REP prefix (restricted cache move feature, see PFXLOCK, bits [15:0]).
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33234H CPU Core Register Descriptions DM_PFLOCK_MSR Bit Descriptions Bits Name Description 63:48 PFLOCKT2 Prefetch Lockout of PREFETCHT2. Bit mask of ways that cannot be allocated or replaced on a data prefetch miss on a PREFECTHT2 instruction. If all ways are locked, PREFETCHT2 is effectively disabled. Use this field to prevent data prefetch operations from polluting too much of the cache. (Default = 0) 47:32 PFLOCKT1 Prefetch Lockout of PREFETCHT1.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions RCONF_E0_FF_MSR Bit Descriptions Bit Name Description 63:56 RPFC Region Properties for 000FC000-000FFFFF. 55:48 RPF8 Region Properties for 000F8000-000FBFFF. 47:40 RPF4 Region Properties for 000F4000-000FAFFF. 39:32 RPF0 Region Properties for 000F0000-000F3FFF. 31:24 RPEC Region Properties for 000EC000-000EFFFF. 23:16 RPE8 Region Properties for 000E8000-000EBFFF. 15:8 RPE4 Region Properties for 000E4000-000E7FFF.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions Region Properties The region properties consist of an 8-bit field as shown in Table 5-15. Table 5-16 and Table 5-17 describe the various region properties effects on read and write operations. Note that the cache is always interrogated even in regions that are not cacheable, and read hits are serviced from the cache while write hits update the cache and are sent to the bus using the region’s write semantics. Table 5-15.
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33234H CPU Core Register Descriptions Table 5-17. Write Operations vs. Region Properties (Continued) WS WC WT WP WA CD 1 1 0 0 0 1 Description Write-combined (uncacheable). Writes to the same cache line may be combined. Multiple writes to the same byte results in a single write with the last value specified. Write order is not preserved; ideal for use with frame buffers. Write-serialize.
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33234H CPU Core Register Descriptions 5.5.2.74 x86 Control Registers MSRs (CR1, CR2, CR3, CR4) These are the standard x86 Control Registers CR1, CR2, CR3, and CR4. CR0 is located at MSR 00001420h (see Section 5.5.2.50 on page 149). The contents of CR0-CR4 should only be accessed using the MOV instruction. They are mentioned here for completeness only. See Section 5.4.
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33234H CPU Core Register Descriptions 5.5.2.76 Data Cache Data MSR (DC_DATA_MSR) MSR Address 00001891h Type R/W Reset Value 00000000_00000000h DC_DATA_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 DC_DATA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DC_DATA DC_DATA_MSR Bit Descriptions Bit 63:0 Name Description DC_DATA Data Cache Data.
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33234H CPU Core Register Descriptions DC_TAG_MSR Bit Descriptions (Continued) Bits 49:32 Name Description LRU Least Recently Used Value. (Default = 0) Bit 49: Ways 11-8 more recent than ways 15-12. Bit 48: Ways 7-4 more recent than ways 15-12. Bit 47: Ways 7-4 more recent than ways 11-8. Bit 46: Ways 3-0 more recent than ways 15-12. Bit 45: Ways 3-0 more recent than ways 11-8. Bit 44: Ways 3-0 more recent than ways 7-4. Bit 43: Ways 15-14 more recent than ways 13-12.
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33234H CPU Core Register Descriptions 5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR) MSR Address 00001894h Type WO Reset Value 00000000_xxxxxxxxh The SNOOP_MSR provides a mechanism for injecting a “snoop-for-write” request into the memory subsystem. Both the I and D caches are snooped for the specified physical address. A hit to a dirty line in the D cache results in a writeback followed by the line being invalidated. A hit to a clean line results in only an invalidation.
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33234H CPU Core Register Descriptions 5.5.2.81 L1 Data TLB Least Recently Used MSR (L1DTLB_LRU_MSR) MSR Address 00001899h Type R/W Reset Value 00000000_00000000h L1DTLB_LRU_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 LRU L1DTLB_LRU_MSR Bit Descriptions Bits Name Description 63:18 RSVD (RO) Reserved (Read Only).
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions L2TLB_INDEX_MSR Bit Descriptions (Continued) Bit Name Description 15:6 RSVD (RO) Reserved (Read Only). (Default = 0) 5:0 INDEX DTE/PTE Index. Increments on every access to L2TLB_ENTRY_I_MSR (MSR 0000189Fh). 5.5.2.
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33234H CPU Core Register Descriptions L2TLB_LRU_MSR Bit Descriptions (Continued) Bits 21:16 Name Description PTE_LRU 4M PTE Least Recently Used Value. Bit 21: 4M PTE entry 0 more recent than entry 1. Bit 20: 4M PTE entry 0 more recent than entry 2. Bit 19: 4M PTE entry 0 more recent than entry 3. Bit 18: 4M PTE entry 1 more recent than entry 2. Bit 17: 4M PTE entry 1 more recent than entry 3. Bit 16: 4M PTE entry 2 more recent than entry 3.
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33234H CPU Core Register Descriptions L2TLB_ENTRY_MSR Bit Descriptions (Continued) Bit Name Description 7 RSVD (RO) Reserved (Read Only). 6 DIRTY Dirty Flag. A 1 indicates that the page has been written to. 5 ACC Accessed Flag. A 1 indicates an entry in the TLB. 4 CD Cache Disable Flag. A 1 indicates that the page is uncacheable. 3 WT_BR Write-Through/Write Burst Flag. When the page is cacheable, a 1 indicates that the page is write-through.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions DM_BIST_MSR Bit Descriptions Bits Name Description 5 RETEN_TLB L2 TLB Retention Timer. Enable retention timer for L2 TLB BIST. 0: Disable. 1: Enable. 4 RUN_TLB L2 TLB Run. Start BIST test on L2 TLB arrays. Should read as 0 because BIST will have completed before the MSR read can start. 3 RETEN_DATA Cache Data Retention Timer. Enable retention timer for cache data array BIST. 0: Disable. 1: Enable. 2 RUN_DATA Cache Data Run.
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33234H CPU Core Register Descriptions BC_CONFIG0_MSR Bit Descriptions (Continued) Bit Name Description 19:14 RSVD Reserved. Write as read. CLK_ONS CPU Core Clocks On during Suspend. 13 0: All CPU Core clocks off during Suspend. (Default) 1: All CPU Core clocks on during Suspend. 12 SUSP Suspend Active. Enable Suspend input. 0: Ignore Suspend input. (Default) 1: Enable Suspend input. 11:9 8 RSVD Reserved. Write as read. RTSC_SUSP Real Time Stamp Counter Counts during Suspend. 0: Disable.
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33234H CPU Core Register Descriptions 5.5.2.91 Reserved Status MSR (RSVD_STS_MSR) MSR Address 00001904h Type RO Reset Value 00000000_00000000h RSVD_STS_MSR Bit Descriptions Bit 63:0 Name Description RSVD (RO) Reserved (Read Only). Reads back as 0. 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.93 Real Time Stamp Counter MSR (RTSC_MSR) MSR Address 00001910h Type R/W Reset Value 00000000_00000000h RTSC_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RTSC (High DWORD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTSC (Low DWORD) RTSC_MSR Bit Descriptions Bit Name Description 63:0 RTSC Real Time Stamp Counter.
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33234H CPU Core Register Descriptions 5.5.2.95 L2 Cache Configuration MSR (L2_CONFIG_MSR) MSR Address 00001920h Type R/W Reset Value 00000000_0000000Eh L2_CONFIG_MSR controls the behavior of the L2 cache.
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33234H CPU Core Register Descriptions 5.5.2.96 L2 Cache Status MSR (L2_STATUS_MSR) MSR Address 00001921h Type RO Reset Value 00000000_00000001h L2_STATUS_MSR returns the status of the L2 cache controller.
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33234H CPU Core Register Descriptions 5.5.2.98 L2 Cache Data MSR (L2_DATA_MSR) MSR Address 00001923h Type R/W Reset Value 00000000_00000000h L2_DATA_MSR is used to access the L2 cache data for diagnostic accesses.
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33234H CPU Core Register Descriptions 5.5.2.100 L2 Cache Tag with Increment MSR (L2_TAG_I_MSR) MSR Address 00001925h Type R/W Reset Value 00000000_00000000h The L2_TAG_I_MSR has the auto incremented L2 cache tag, MRU and valid bits for diagnostic accesses.
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33234H CPU Core Register Descriptions L2_BIST_MSR Bit Descriptions (Continued) Bit Name Description 10 BIST_TAG_GO_ WAY3 (RO) L2 Cache Tag BIST Way 3 Result (Read Only). BIST_TAG_GO_ WAY2 (RO) L2 Cache Tag BIST Way 2 Result (Read Only). BIST_TAG_GO_ WAY1 (RO) L2 Cache Tag BIST Way 1 Result (Read Only). BIST_TAG_GO_ WAY0 (RO) L2 Cache Tag BIST Way 0 Result (Read Only). BIST_TAG_GO (RO) L2 Cache Tag BIST Result (Read Only).
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.103 Power Mode MSR (PMODE_MSR) MSR Address 00001930h Type R/W Reset Value 00000000_00000300h This MSR enables some modules to turn their clocks off when they are idle to save power. Most of these bits are off by default. It is recommended that they be set by BIOS.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.106 Bus Controller Extended Debug Registers 6 and 7 MSR (BXDR6_BXDR7_MSR) MSR Address 00001953h Type R/W Reset Value 00000000_00000000h BXDR6 (bits [31:0]) contains the status of the extended bus controller breakpoints. When a breakpoint occurs, the corresponding status bit is set in this register. The status bits remain set until cleared by an MSR write. BXDR7 (bits [63:32]) is used to enable and specify the type of BXDR0-BXDR3.
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33234H CPU Core Register Descriptions BXDR6_BXDR7_MSR Bit Descriptions (Continued) Bit Name Description 41:40 LEN0 Extended Breakpoint 0 Length. Selects the size of extended breakpoint 1. See LEN3 (bits [47:46]) for decode. E3 Extended Breakpoint 3 Enable. Allows extended breakpoint 3 to be enabled. 35 0: Disable. 1: Enable. 34 E2 Extended Breakpoint 2 Enable. Allows extended breakpoint 2 to be enabled. 0: Disable. 1: Enable. 33 E1 Extended Breakpoint 1 Enable.
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33234H CPU Core Register Descriptions 5.5.2.107 Bus Controller Debug Registers 0 through 3 MSRs Each of these registers specifies an address that must match the physical address currently in the bus controller in order to trigger the breakpoint. BDR7 is used to enable and specify the type of BDR0-BDR3. If a breakpoint is configured as a memory breakpoint, the address is matched on a QWORD granularity. If a breakpoint is configured as an I/O or MSR breakpoint, the address is matched based on all 32 bits.
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33234H CPU Core Register Descriptions 5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR) MSR Address 00001976h Type R/W Reset Value 00000000_00000000h This register contains the status of the bus controller breakpoints. When a breakpoint occurs, the corresponding status bit is set in this register. The status bits remain set until cleared by an MSR write.
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33234H CPU Core Register Descriptions BDR7_MSR Bit Descriptions Bit Name Description 31:28 TYPE3 Breakpoint 3 Type. Selects the type of extended breakpoint 3. 0000: IM memory read (Default). 0001: DM memory read. 0010: DM memory write. 0011: DM memory read/write. 0100: DM I/O read. 0101: DM I/O write. 0110: DM I/O read/write. 0111: GLBus snoop for read. 1000: GLBus snoop for write. 1001: GLBus snoop for write-invalidate. 1010: MSR read. 1011: MSR write.
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33234H CPU Core Register Descriptions 5.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR) MSR Address 00001980h Type R/W Reset Value 00000000_00000000h The MSRs at addresses 00001980h-00001983h provide alternate array delay control values for the MSS arrays. After a reset, the MSS clock modules provide JTAG-accessible control values. These MSRs can be used by software to override these values.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.114 FPU Modes MSR (FP_MODE_MSR) MSR Address 00001A00h Type R/W Reset Value 00000000_00000000h FP_MODE_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 9 8 7 6 5 4 3 2 1 0 FPU_IPE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FPU_SP RSVD FP_MODE_MSR Bit Descriptions Bit Name Description 63:2 RSVD Reserved. Write as read.
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33234H CPU Core Register Descriptions 5.5.2.117 FPU x87 Control Word MSR (FPU_CW_MSR) MSR Address 00001A10h Type R/W Reset Value 00000000_00000040h FPU_CW_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSVD 6 5 4 3 2 1 0 FPU_CW FPU_CW_MSR Bit Descriptions Bit Name Description 63:12 RSVD Reserved. Write as read. 11:0 FPU_CW FPU Control Word.
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33234H CPU Core Register Descriptions FPU_TW_MSR Bit Descriptions Bit Name Description 63:16 RSVD Reserved. Write as read. 15:0 FPU_TW FPU Tag Word. 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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33234H CPU Core Register Descriptions 5.5.2.
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CPU Core Register Descriptions 33234H 5.5.2.124 FPU Reserved MSRs (FPU_RSVD_MSR) MSR addresses 00001A60h through 00001A6F are reserved for internal storage purposes and should not be written to. 5.5.2.
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33234H CPU Core Register Descriptions CPUIDx_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 CPUIDx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPUIDx CPUIDx_MSR Bit Descriptions Bit Name Description 63:0 CPUID0 Standard Levels and Vendor ID String 1. Same data as CPUID instruction [00000000] EBX/EAX. 63:0 CPUID1 Vendor ID Strings 2 and 3.
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Integrated Functions 33234H 6 6.0Integrated Functions The integrated functions of the AMD Geode™ LX processor are: • GeodeLink™ Memory Controller (GLMC) • GeodeLink PCI Bridge (GLPCI) • Video Input Port (VIP) • Security Block (SB) • Graphics Processor (GP) This section provides a functional description of each module and its respective registers.
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33234H 6.1 GeodeLink™ Memory Controller GeodeLink™ Memory Controller The GeodeLink™ Memory Controller (GLMC) module supports the Unified Memory Architecture (UMA) of the AMD Geode™ LX processor and controls a 64-bit DDR SDRAM interface without any external buffering. The internal block diagram of the GLMC is shown in Figure 6-2. The SDRAM memory array contains both the main system memory and the graphics frame buffer. Up to four module banks of SDRAM are supported.
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33234H GeodeLink™ Memory Controller Features • Supports up to 400 MT/S (million transfers per second) DDR SDRAMs • Supports 64-bit data interface Internal aaaaaaaaaaaaaaaaaaaaaaaaaa Physical 22222222211111111110000000 Address 87654321098765432109876543 • Supports unbuffered DIMMs and SODIMMs • Can maintain up to 16 open banks at a time • Can support up to three outstanding requests at a time • Arbiter reorders requests from different sources to optimize data bus utilization • Single and burst data phase
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33234H Auto Low Order Interleaving The GLMC requires that module banks [0:1], if both installed, be identical and module banks [2:3], if both installed, be identical. Standard DIMMs and SODIMMs are configured this way. Because of this requirement, when module banks [0:1] are installed or module banks [2:3] are installed, LOI is in effect, when enabled for those bank pairs. If all four module banks [0:3] are identical, then LOI is in effect across all four module banks.
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33234H GeodeLink™ Memory Controller Table 6-1.
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33234H GeodeLink™ Memory Controller Table 6-3.
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33234H GeodeLink™ Memory Controller 6.1.1.2 Arbitration The pipelining of the GLMC module requests consists of the GLIU0 interface request plus two request buffers: the C (closed) and O (open) slots (see Figure 6-7). A request is accepted at the GLIU0 interface as long as there is a slot available. The C slot holds a request to a closed page, or a request to an open page that matches a row address. The O slot holds a request to an open page that matches a row address.
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33234H GeodeLink™ Memory Controller 6.1.1.3 Data Path The write datapath utilizes three write buffers to gather write data within a burst, each one is 4 deep x 64 bits. Writes to the buffers are alternated between the three buffers or whichever one is empty. The SID, PID, and implied BEX are also buffered along with the write data.
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33234H GeodeLink™ Memory Controller mph1 rqin_ready rqin_take WRREQX rqin WRREQY dain_ready dain_take dain wrx0 wrx1 wrx2 wrx3 wry0 drdywx drdyrx wrx0 wrx1 wrx2 wrx3 wry0 wrx1 wrx2 wrx3 w_databuf_out w_dataf m_sd_data wrx0 wrx0 wrx1 wrx2 wry0 wrx3 wry0 m_sd_dqs daout wrrespx wrrespy Figure 6-9.
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33234H 6.1.2 Power Control The GLMC employs some methods of power control for power savings. One method is that it TRI-STATEs the GLMC address and control pins when there is no valid address or control data being driven (i.e., when all the chip selects are inactive (high). This feature is enabled via GLMC MSR 2000001Dh[12] (TRI_STATE_DIS), and is disabled by default. The second and third methods of power control are effected via the GLMC’s GLD_MSR_PM register (MSR 20002004h).
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2 GeodeLink™ Memory Controller Register Descriptions All GLMC registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instructions. tables that include reset values and page references where the bit descriptions are provided. Note: The registers associated with the GLMC are the Standard GeodeLink Device (GLD) MSRs and GLMC Specific MSRs.
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33234H GeodeLink™ Memory Controller Register Descriptions Table 6-6. GLMC Specific MSR Summary MSR Address Type 2000001Fh --- 20000020h R/W 6.2.1 Register Name Reset Value Reference --- --- 00000000_00000006h Page 236 Reserved PM Sensitivity Counters (MC_CF_PMCTR) Standard GeodeLink™ Device (GLD) MSRs 6.2.1.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.1.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.1.5 GLD Power Management (GLD_MSR_PM) MSR Address 20002004h Type R/W Reset Value 00000000_00000000h GLD_MSR_PM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 8 7 6 5 4 3 2 1 0 PM0 9 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PM1 RSVD GLD_MSR_PM Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only).
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2 GLMC Specific MSRs 6.2.2.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2.
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33234H GeodeLink™ Memory Controller Register Descriptions MC_CF07_DATA Bit Descriptions (Continued) Bit Name Description 36 D0_CB DIMM0 Component Banks. Number of component banks per module bank for DIMM0. 0: 2 Component banks. (Default) 1: 4 Component banks. 35 34:32 RSVD Reserved. D0_PSZ DIMM0 Page Size. 000: 1 KB 001: 2 KB 010: 4 KB 011: 8 KB 100: 16 KB 101: 32 KB 110: Reserved 111: DIMM0 Not Installed (Default) 31:30 RSVD Reserved. 29:28 MSR_BA Mode Register Set Bank Address.
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33234H GeodeLink™ Memory Controller Register Descriptions MC_CF07_DATA Bit Descriptions (Continued) Bit Name Description 2 RSVD Reserved. 1 SOFT_RST Software Reset. Puts the GLMC in a known state. Does not change configuration registers. The recommended sequence to use is: 1) Make sure SDRAM interface has “been idle for a while”. 2) Set software reset, then clear software reset. 3) Do a refresh cycle. Accesses to memory may resume as normal following this.
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33234H GeodeLink™ Memory Controller Register Descriptions MC_CF8F_DATA Bit Descriptions Bit Name Description 63:56 STALE_REQ GLIU Max Stale Request Count. Non-high priority requests (PRI = 0) are made high-priority requests when the request is not serviced within max stale request count clocks. (Default = 18h) 55:53 RSVD Reserved. 52:51 XOR_BIT_SEL XOR Bit Select. Selects which upper GLIU address bit to XOR with MB0, BA1 or BA0 (see "Auto Low Order Interleaving" on page 212).
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33234H GeodeLink™ Memory Controller Register Descriptions MC_CF8F_DATA Bit Descriptions (Continued) Bit Name Description 11:8 ACT2ACT ACT(0) to ACT(1) Period. tRRD. Minimum number of SDRAM clocks between ACT and ACT command to two different component banks within the same module bank. (Default = 7h) 7:6 DPLWR Data-in to PRE Period. tDPLW. Minimum number of clocks from last write data to precharge command on the same component bank. (3..1 valid). Default = 10) 5:4 DPLRD Data-in to PRE Period.
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33234H GeodeLink™ Memory Controller Register Descriptions MC_CF1017_DATA Bit Descriptions Bit Name Description 2:0 WR2DAT Write Command To Data Latency. Number of clocks between the write command and the first data beat. Valid values are: [2,1,0], and must correspond to the installed DIMMs as follows: 0h: No delay. 1h: 1-clock delay for DDR unbuffered DIMMs. (Default) 6.2.2.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2.
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33234H GeodeLink™ Memory Controller Register Descriptions MC_CFCLK_DBUG Bit Descriptions Bit Name Description 63:35 RSVD Reserved. 34 B2B_DIS Back-to-Back Command Disable. Setting this bit disables the issuing of DRAM commands within back-to-back cycles in both MTEST and normal functional mode.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2.15 Page Open Status (MC_CFPG_OPEN) MSR Address 2000001Eh Type RO Reset Value 00000000_0000FFFFh MC_CFPG_OPEN Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD PGOPEN1 9 8 7 6 5 4 3 2 1 0 PGOPEN0 MC_CFPG_OPEN Bit Descriptions Bit Name Description 63:16 RSVD Reserved. Reads back as 0.
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33234H GeodeLink™ Memory Controller Register Descriptions 6.2.2.17 PM Sensitivity Counters (MC_CF_PMCTR) MSR Address 20000020h Type R/W Reset Value 00000000_00000006h MC_CF_PMCTR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PM1_SENS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PM0_SENS MC_CF_PMCTR Bit Descriptions Bit Name Description 63:32 PM1_SENS PMode1 Sensitivity Counter.
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33234H Graphics Processor 6.3 Graphics Processor The Graphics Processor is based on the graphics processor used in the AMD Geode™ GX processor with several features added to enhance performance and functionality.
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33234H Graphics Processor Table 6-7.
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33234H Graphics Processor 6.3.1 Command Buffer tiate an action in the processor by writing a command buffer structure into memory at the write address (GP_CMD_WRITE), then updating the write address to point to the next available space in the command buffer, either the next contiguous DWORD address, or the buffer starting address (GP_CMD_TOP) if the wrap bit is set in the command buffer control word. Command buffers are allowed to wrap around the end of the command buffer space (i.e.
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33234H Graphics Processor Table 6-9. Vector Command Buffer Structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 W 0 1 S 9 8 RSVD 7 6 5 4 3 2 1 0 4 3 2 1 0 Write Enables GP_RASTER_MODE Data GP_DST_OFFSET Data GP_VEC_ERR Data GP_STRIDE Data GP_VEC_LEN Data GP_SRC_COLOR_FG Data GP_PAT_COLOR_0 Data GP_PAT_COLOR_1 Data GP_PAT_DATA_0 Data GP_PAT_DATA_1 Data GP_CH3_MODE_STR Data GP_BASE_OFFSET Data GP_VECTOR_MODE Data Table 6-10.
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33234H Graphics Processor Where: Table 6-12. Bit Descriptions Name Description WE Write Enable. One bit for each of the required DWORDs which follow in the command buffer. A set bit indicates that the field is valid and should be updated in the GP. A clear bit indicates the field should be skipped. W Wrap Bit. If set, then return to the top of command buffer space after executing this buffer. S Stall Bit. Execution of this command will be stalled until the GP’s pipeline is empty.
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33234H 6.3.2.1 Rotating BLTs This feature of the GP allows bitmaps to be rotated 90°, 180° or 270°. The 90° and 270° modes work by reading vertical strips of the source bitmap that are one cache line (32 bytes) wide starting at either the top right or bottom left corner of the bitmap. The output is written as tiles that are one cache line wide by either 8, 16 or 32 pixels tall, depending on the color depth of the input data stream.
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33234H Graphics Processor 6.3.2.4 Palletized Color Support If the Preserve LUT Data bit is set in the GP_CH3_MODE_STR register (GP Memory Offset 64h[20]) then 1K of the 2K buffer space will be allocated to be a LUT. As long as this bit remains set, the LUT data is preserved as written. Setting this bit has the impact of slightly lowering performance since it limits the prefetch ability of the GP, or its ability to receive massive amounts of host source data.
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33234H Graphics Processor 6.3.2.5 Anti-Aliased Text Support Channel 3 can be setup to fetch 4-bpp alpha channel data that can be combined with either 16 or 32-bpp color or monochrome source data using the alpha unit in the GP. The depth and type in the GP_CH3_MODE_STR register should be setup to indicate 4-bpp alpha and the AS bits in the GP_RASTER_MODE register (GP Memory Offset 38h[19:17]) should be set to 110 to select the alpha from channel 3. 6.3.2.
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33234H Graphics Processor 6.3.2.8 Channel 3 Host Source Channel 3 also supports host source data writes. When the HS bit is set in the GP_CH3_MODE_STR register (GP Memory Offset 64h[18]), the channel 3 fetch engine is disabled and the FIFOs are filled via register writes to the GP_CH3_HSRC register (GP Memory Offset 6Ch) or its aliased space.
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33234H 6.3.4 Vector Operation Graphics Processor 6.3.6 Pattern Generation Generating a vector requires a similar setup to a BLT. Registers must be written to specify the X and Y offsets of the starting position of the vector within the frame buffer, the vector length, and the three error terms required by the Bresenham algorithm. In addition, any pattern colors and pattern data should be loaded before initiating the vector. Source data is not fetched when rendering vectors.
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33234H Graphics Processor 6.3.6.2 Color Patterns Color patterns are enabled by selecting the color pattern mode in the GP_RASTER_MODE register (GP Memory Offset 38h). In this mode, both of the GP_PAT_DATA registers and all six of the GP_PAT_COLOR registers are combined to provide a total of 256 bits of pattern. The number of lines that the pattern can hold is dependent upon the number of bits per pixel.
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33234H Graphics Processor Table 6-17.
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33234H Graphics Processor 6.3.7 8x8 Color Patterns GP_RASTER_MODE register (GP Memory Offset 38h[31:28]), then the pattern is translated to the depth specified by the GP_RASTER_MODE register. The new channel 3 hardware provides the capability of performing BLTs with 64 pixel color patterns at all color depths. To setup this mode, software first loads the pattern data into the LUT beginning at address 100h The least significant byte of this first DWORD contains the upper left most pixel of the pattern.
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33234H Graphics Processor 6.3.8.2 Host Source For source data that is not already in the frame buffer region of memory, software can use the GP_HST_SRC register (GP Memory Offset 48h) for loading the data into the Graphics Processor. This is achieved by selecting host source as the origination of the source data when setting up the BLT.
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33234H Graphics Processor 6.3.8.3 Source Expansion The Graphics Processor contains hardware support for color expansion of monochrome source data. Those pixels corresponding to a clear bit in the source data are rendered using the color specified in the GP_SRC_COLOR_BG register (GP Memory Offset 14h), and the pixels that are set in the source data are rendered using the color specified in the GP_SRC_COLOR_FG register (GP Memory Offset 10h). 6.3.8.
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33234H 6.3.11 Graphics Processor Image Compositing Using Alpha Whereas the raster operation allows different streams of data to be logically combined, alpha channel composition allows two streams of data to be mathematically combined based on the contents of their alpha channel, which is an additional channel to the red, blue, and green data contained in the stream.
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33234H Graphics Processor Table 6-27. Alpha Blending Modes (Continued) FA FB A over B 1 1-αΑ A in B αB B held out by A A stop B Operation A xor B darken A Diagram AS Bits OS Bits Display image A on top of image B. Wherever image A is transparent, display image B. 000 10 0 Use image B to mask image A. Wherever image B is non-transparent, display image A. 001 00 0 1-αA Use image A to mask image B. Wherever image A is transparent, display image B.
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33234H 6.4 Graphics Processor Register Definitions Graphics Processor Register Definitions The registers associated with the Graphics Processor (GP) are the Standard GeodeLink™ Device (GLD) MSRs and Graphics Processor Configuration registers. Table 6-28 and Table 6-29 are register summary tables that include reset values and page references where the bit descriptions are provided.
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33234H Graphics Processor Register Definitions Table 6-29.
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33234H 6.4.1 Graphics Processor Register Definitions Standard GeodeLink™ Device (GLD) MSRs 6.4.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address A0002000h Type RO Reset Value 00000000_0003D4xxh This MSR contains the revision and device IDs for the particular implementation of the Graphics Processor. This register is read only.
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33234H Graphics Processor Register Definitions 6.4.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address A0002002h Type R/W Reset Value 00000000_00000000h This MSR contains the SMI and Mask bits for the GP. An SMI is asserted whenever an illegal address or an illegal type is detected on the GLIU and the mask bit is not set. This also causes the mb_p_asmi output to be asserted. This signal remains asserted until the SMI is cleared or the mask bit is set.
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33234H Graphics Processor Register Definitions GLD_MSR_ERROR Bit Descriptions Bit Name Description 63:18 RSVD Reserved. Read returns 0. 17 AE Address Error. 1 indicates address violation. Write = 1 clears bit, write = 0 has no effect. 16 TE Type Error. 1 indicates type error. Write = 1 clears bit, write = 0 has no effect. RSVD Reserved. Read returns 0. 1 AM Address Mask. Ignore address violations when set. 0 TM Type Mask. Ignore type violations when set. 15:2 6.4.1.
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33234H Graphics Processor Register Definitions 6.4.2 Graphics Processor Configuration Registers 6.4.2.1 Destination Offset (GP_DST_OFFSET) GP Memory Offset 00h Type R/W Reset Value 00000000h GP_DST_OFFSET is used to give a starting location for the destination of a BLT or vector in the destination region of memory. It consists of three fields, the OFFSET, XLSBS and YLSBS.
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33234H Graphics Processor Register Definitions GP_SRC_OFFSET Bit Descriptions (Continued) Bit Name Description 25:24 RSVD Reserved. Write as read. 23:0 OFFSET Offset. Offset from the source base address to the first source pixel. 6.4.2.3 Vector Error (GP_VEC_ERR) GP Memory Offset 04h Type R/W Reset Value 00000000h This register specifies the axial and diagonal error terms used by the Bresenham vector algorithm.
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33234H Graphics Processor Register Definitions GP_STRIDE Bit Descriptions Bit Name Description 31:16 S_STRIDE Source Stride. Width of the source bitmap (in bytes). 15:0 D_STRIDE Destination Stride. Width of the destination scan line (in bytes). 6.4.2.5 BLT Width/Height (GP_WID_HEIGHT) GP Memory Offset 0Ch Type R/W Reset Value 00000000h This register is used to specify the width and the height of the BLT in pixels.
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33234H Graphics Processor Register Definitions 6.4.2.7 Source Color Foreground (GP_SRC_COLOR_FG) GP Memory Offset 10h Type R/W Reset Value 00000000h When source data is monochrome, the contents of this register are used for expanding pixels that are set in the monochrome bitmap, thus replacing the monochrome bit with a color that is appropriately sized for the destination. When source data is color, this register contains the color key for transparency.
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33234H Graphics Processor Register Definitions 6.4.2.8 Source Color Background (GP_SRC_COLOR_BG) GP Memory Offset 14h Type R/W Reset Value 00000000h When source data is monochrome, the contents of this register are used for expanding pixels that are clear in the monochrome bitmap, thus replacing the monochrome bit with a color that is appropriately sized for the destination. When source data is color, this register contains the color key mask for transparency.
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33234H Graphics Processor Register Definitions 6.4.2.9 Pattern Color (GP_PAT_COLOR_x) GP Memory Offset 18h GP_PAT_COLOR_0 1Ch GP_PAT_COLOR_1 20h GP_PAT_COLOR_2 24h GP_PAT_COLOR_3 28h GP_PAT_COLOR_4 2Ch GP_PAT_COLOR_5 Type R/W Reset Value 00000000h In solid pattern mode, the pattern hardware is disabled and GP_PAT_COLOR_0 is selected as the input to the raster operation. In monochrome pattern mode, GP_PAT_COLOR_0 and GP_PAT_COLOR_1 are used for expanding the monochrome pattern into color.
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33234H Graphics Processor Register Definitions 6.4.2.10 Pattern Data (GP_PAT_DATA_x) GP Memory Offset 30h GP_PAT_DATA_0 34h GP_PAT_DATA_1 Type R/W Reset Value 00000000h In solid pattern mode, these registers are not used. In monochrome pattern mode, GP_PAT_DATA_0 and GP_PAT_DATA_1 combine to hold the entire 8x8 pattern (64 bits). GP_PAT_DATA_0[7:0] is the first line of the pattern, with bit 7 corresponding to the leftmost pixel on the screen. GP_PAT_DATA_1[31:24] is the last line of the pattern.
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33234H Graphics Processor Register Definitions GP_RASTER_MODE Bit Descriptions Bit 31:28 Name Description BPP/FMT Color Depth and Format. 0000: 8-bpp, 3:3:2 format. 0100: 16-bpp, 4:4:4:4 format. 0101: 16-bpp, 1:5:5:5 format. 0110: 16-bpp, 0:5:6:5 format. 1000: 32-bpp, 8:8:8:8 format. All Others: Undefined. 27:24 RSVD 23:22 EN Reserved. Write as read. Alpha Enable Bits. Also used to select how to apply the specified operation. 00: Alpha disabled/ROP enabled.
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33234H Graphics Processor Register Definitions GP_RASTER_MODE Bit Descriptions (Continued) Bit Name Description 7:0 ROP/aR Raster Operations (ROP). Combination rule for source, pattern and destination when performing raster operations. (See Section 6.3.10 "Raster Operations (ROP)" on page 251.) Alpha Value (aR). Alpha value that can be used for some of the alpha compositing operations. 6.4.2.
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33234H Graphics Processor Register Definitions 6.4.2.13 BLT Mode (GP_BLT_MODE) GP Memory Offset 40h Type WO Reset Value 00000000h Writing to this register configures the BLT mode and initiates the rendering of the BLT. If a BLT or vector operation is already in progress when this register is written, the BLT pending bit in GP_BLT_STATUS (GP Memory Offset 44h) is set and the BLT is queued to begin when the current operation is complete.
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33234H Graphics Processor Register Definitions 6.4.2.14 Status and Reset (GP_BLT_STATUS, GP_RESET) GP Memory Offset 44h Type RO Reset Value 00000008h This register is used to provide software with the current status of the GP in regards to operations pending and currently executing. A write to this register has no effect unless byte 3 is 69h, which causes a reset of the GP, losing all state information and discarding any active or pending BLT or vector.
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33234H Graphics Processor Register Definitions GP_HST_SRC Bit Descriptions Bit 31:0 Name Description HST_SRC Host Source Data. Used during BLT in host source mode. 6.4.2.16 Base Offset (GP_BASE_OFFSET) GP Memory Offset 4Ch Type R/W Reset Value 01004010h This register is used to define the physical base addresses of the regions used for all GP read and write operations to memory. Each base defines a 16 MB region that begins on a 4 MB boundary.
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33234H Graphics Processor Register Definitions 6.4.2.18 Command Bottom (GP_CMD_BOT) GP Memory Offset 54h Type R/W Reset Value 00FFFFE0h This register defines the ending address of the command buffer within the command buffer region. Bits [23:0] of this register are combined with the CBASE in GLD_MSR_CONFIG (MSR A0002001h) to form the 32 bit address.
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33234H Graphics Processor Register Definitions 6.4.2.20 Command Write (GP_CMD_WRITE) GP Memory Offset 5Ch Type R/W Reset Value 00000000h This register points to the next location to be written with command buffer data from the processor. After the processor writes out a complete command buffer starting at this address, it should write to this register to update the value to point to the next location to be written.
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33234H Graphics Processor Register Definitions GP_CH3_OFFSET Bit Descriptions Bit Name Description 31:29 YLSBS YLSBS. Y coordinate of starting pixel within color pattern memory. 28:26 XLSBS XLSBS. X coordinate of starting pixel within color pattern memory. 25 N Nibble Select. Nibble address for 4-bpp pixels/alpha. 0 starts at the leftmost nibble, 1 starts at the rightmost. 24 RSVD Reserved. Write as read. OFFSET Offset. Offset from the channel 3 base address to the first source pixel.
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33234H Graphics Processor Register Definitions GP_CH3_MODE_STR Bit Descriptions (Continued) Bit Name Description 29 X X Direction for Fetch. Data is reversed if fetch direction does not match destination direction. 0: Left to right direction. 1: Right to left direction. 28 Y Y Direction for Fetch. Data is reversed if fetch direction does not match destination direction. 0: Top to bottom direction. 1: Bottom to top direction. 27:24 BPP/FMT Color Depth and Format of Input. 0000: 8-bpp 3:3:2.
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33234H Graphics Processor Register Definitions 6.4.2.23 Width/Height (GP_CH3_WIDHI) GP Memory Offset 68h Type R/W Reset Value 00000000h This register is used to specify the width and the height of the bitmap to be fetched on channel 3 in pixels. This need not match the destination width and height, as in the case of a rotation BLT where the width and height are swapped, but the total number of pixels should be equal to the number of pixels in the destination.
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33234H Graphics Processor Register Definitions 6.4.2.25 LUT Index (GP_LUT_INDEX) GP Memory Offset 70h Type R/W Reset Value 00000000h This register is used to initialize the LUT_INDEX pointer that is used for subsequent LUT operations. All LUT accesses are DWORD accesses so only the 9 LSBs of the pointer are used to index into the 2 KB LUT. Addresses 000h-0FFh are used for 8-bit indexed LUT data. Addresses 000h-00Fh are used for 4-bit indexed LUT data.
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33234H Graphics Processor Register Definitions 6.4.2.27 Interrupt Control (GP_INT_CNTRL) GP Memory Offset 78h Type R/W Reset Value 0000FFFFh This register is used to control the interrupt signal from the GP. It contains a 16-bit mask and a 16-bit interrupt detect. The mask portion is read/write. A bit set in the mask register disables the corresponding interrupt bit. At reset, all interrupts are disabled.
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33234H 6.5 Display Controller Display Controller The Display Controller (DC) module retrieves graphics, video, and overlay streams from the frame buffer, serializes the streams, performs any necessary color lookups and output formatting, and interfaces to the VP for driving the display device.
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33234H Display Controller The GUI block, shown in Figure 6-13, provides sophisticated graphics functionality suitable for a GUI environment such as Windows® XP, Windows CE, or Linux® operating Compressed Line Buffer (64x64-bit) systems. The GUI is optimized for high resolution and high color depth display modes.
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33234H Display Controller The VGA block, shown in Figure 6-14, provides hardware support for a compatible VGA solution. It consists of an independent CRT controller and pixel formatting units. It also provides the standard VGA host memory data manip- ulation functions such as color compare, set, reset, etc. This block provides complete support for all VGA text and graphics modes.
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33234H Display Controller 6.5.1 GUI Functional Overview 6.5.1.1 Display Mode Support The display modes listed in Table 6-32 are supported by the GUI block. 32- and 24-bpp display support is provided across all resolutions. The Dot Clock source (DOTCLK) is provided by a PLL. Available memory bandwidth determines the resolutions and color depths that will function without display tearing.
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33234H Display Controller Table 6-32. Display Modes (Continued) Resolution 1280 x 1024 1600 x 1200 1920x1440 Color Depth (bpp) Refresh Rate (Hz) Dot Clock (MHz) Min. GLIU Frequency (MHz) 8, 16, or 24/32 60 108.000 200 8, 16, or 24/32 70 129.600 200 8, 16, or 24/32 72 133.500 200 8, 16, or 24/32 75 135.000 200 8, 16, or 24/32 85 157.500 200 8, 16, or 24/32 90 172.800 400 8, 16, or 24/32 100 192.000 400 8, 16, or 24/32 60 162.000 200 8, 16, or 24/32 70 189.
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33234H Display Controller 6.5.1.2 Display FIFO The DC module incorporates a 512-entry x 64-bit display FIFO that queues up all display data, including graphics frame buffer data, compressed display buffer data, cursor and icon overlay data, and video overlay YUV data. When the video output port is enabled, 32 slots of the display FIFO are allocated for the video transfer buffer. A hardware icon overlay is also supported for applications that require a fixed sprite overlay.
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33234H Display Controller Cursor/Icon Buffer Formats In 2-bpp mode, the cursor buffer is stored as a linear display buffer containing interlaced AND and XOR QWORDs (8-byte segments). Each QWORD contains the appropriate mask for 64 pixels. Even QWORDs contain the AND masks and odd QWORDs contain the XOR masks. The masks are stored “in display order” with the leftmost pixel being most significant and the rightmost pixel being least significant.
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Display Controller 6.5.1.4 Display Refresh Compression To reduce the system memory contention caused by the display refresh, the GUI block contains compression and decompression logic for compressing the frame buffer image in real time as it is sent to the display. The DC does not modify the standard frame buffer, but rather, it utilizes a separate compressed display buffer for updating the display under certain conditions.
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33234H Display Controller 6.5.1.9 Video Overlay Support The GUI block also supports a video overlay function. The DC has flexible addressing capability for YUV 4:2:2 and YUV 4:2:0 display surfaces. Video data is stored in a separate buffer within the off-screen frame buffer. Independent surface pitch control is provided for Y and U/V. The DC fetches the contents of the video and transmits it to the Video Processor once per frame.
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33234H Display Controller 6.5.1.10 Output Formats Video Output Data Sequencing The order that video data is transmitted from the DC to the VP depends on the format of the video data. For YUV 4:2:0 mode, the entire stream of Y data is transmitted for a source line, followed by the entire stream of U data for the line, and finally, the entire stream of V data for the line. The size of the U and V streams are always one-half the size of the Y stream. The data is not interlaced as in the YUV 4:2:2 mode.
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33234H 6.5.4 Display Controller VGA Block Functional Overview Graphics Modes The graphics modes defined by VGA BIOS are shown in Table 6-41. The VGA block provides full hardware support for a VGA graphics subsystem. It is compatible with the IBM VGA as defined in the IBM Video Subsystem Technical Reference manual. This section provides an overview of VGA features and functions. Table 6-39. VGA Text Modes 6.5.4.
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33234H Display Controller 6.5.5.2 Graphics Controller The graphics controller manages the CPU interaction with video memory, and contains the video serializers that feed the front end of the attribute controller. Several memory read and write modes are supported that provide various forms of acceleration for VGA graphics operations. A highlevel diagram of the graphics controller is shown in Figure 6-16.
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33234H Display Controller 6.5.5.3 Write Modes There are four write modes supported by the graphics controller (mode 0, 1, 2, and 3). These write modes provide assistance to the CPU when the frame buffer is in a planar graphics format. Figure 6-17 shows the data flow logic that supports these modes.
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33234H Display Controller 6.5.5.4 Read Modes There are two read modes provided to assist the CPU with graphics operations in planar modes. Read mode 0 simply returns the frame buffer data. Read mode 1 allows the CPU to do a single color compare across eight pixels. Figure 618 shows the data flow for read modes. Figure 6-19 on page 292 shows how the color compare logic in Figure 618 works.
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33234H Display Controller D[7:0] XOR C CCx[7:0] OR E Color Compare Block Detail 31:24 Memory Data [31:0] 3 Color Compare [3:0] Color Don’t Care [3:0] 23:16 2 3 E CC3 D E 7:0 1 2 C 15:8 0 1 C D CC2 0 E C D CC1 E C D CC0 8x4 Input AND Compare Result [7:0] Figure 6-19.
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33234H Display Controller 6.5.6 Graphics Scaler/Filter The DC incorporates a 3x5 tap filter to be used for up/ downscaling of the graphics image. In order to support the filter, three lines of buffering are also included. These three line buffers support a frame buffer resolution of up to 1024 pixels wide. For wider images, the buffers are automatically reconfigured into one line, and scaling is not supported.
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33234H Display Controller Addresses for H. Coefficient RAM from H Phase Adder x + x The entire structure is replicated for each pixel component (red, green, blue, and alpha). x x + x H. Coefficient RAM x X X 2 Pixel Latch + X 2 Pixel Latch X X Figure 6-20.
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33234H Display Controller To support the flicker filter, the scaling filter then feeds two additional line buffers. These buffers are 1024 pixels wide. The scaling filter directly feeds a tap of the 3x1-tap flicker filter. (The other two taps are fed by the two line buffers.) All filtering is performed in the GeodeLink I/F clock domain. The result from the flicker filter feeds a final line buffer, which is used to synchronize the data stream to the Dot clock domain.
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33234H 6.5.7 Color Key Elimination Additional logic, not shown in the diagrams, is used to preserve the color key color. This logic, when enabled, adjusts the alpha value for each filter input pixel in which a color key match is detected. The filter then uses the alpha value to determine if a pixel matches the color key. For information on the interaction of cursor and color key, Table 6-35 on page 284.
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33234H Display Controller 6.5.9 Interlaced Modes For interlaced modes, the V_ACTIVE and V_TOTAL fields are configured for the odd field. The Even Field Vertical Timing registers (DC Memory Offsets 0E4h-0ECh) are configured for the corresponding even field. Figure 6-22 on page 298 shows a representative timing diagram for the odd and even timing register settings in interlaced modes, and Table 6-43 on page 298 presents the (decimal) timing values for some common interlaced modes.
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33234H 6.5.10 Display Controller Interlaced Timing Examples V_Total_Even register settings each define a region that begins in the even field and ends in the next odd field. Figure 6-22 shows how the DC's timing registers are used to control timings for interlaced display modes. The SMTPE standards define the even and odd fields as starting at VSYNC, while the register settings define the timings based on the start of the active display region, as is common in (non-interlaced) VESA timing standards.
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33234H Display Controller Table 6-44.
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33234H 6.6 Display Controller Register Descriptions Display Controller Register Descriptions This section provides information on the registers associated with the Display Controller (DC) (i.e., GUI and VGA blocks), including the Standard GeodeLink™ Device (GLD) MSRs and the Display Controller Specific MSRs (accessed via the RDMSR and WRMSR instructions). Table 6-45 through Table 6-50 are register summary tables that include reset values and page references where the bit descriptions are provided.
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Display Controller Register Descriptions 33234H Table 6-47.
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33234H Display Controller Register Descriptions Table 6-47.
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Display Controller Register Descriptions 33234H Table 6-48. VGA Block Configuration Register Summary DC Memory Offset Type Register Name 100h R/W 104h RO Reset Value Reference VGA Configuration (VGA_CONFIG) 00000000h Page 355 VGA Status (VGA_STATUS) 00000000h Page 355 Table 6-49.
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33234H Display Controller Register Descriptions Table 6-50.
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33234H Display Controller Register Descriptions 6.6.1 Standard GeodeLink™ Device (GLD) Registers (MSRs) 6.6.1.
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33234H Display Controller Register Descriptions 6.6.1.
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Display Controller Register Descriptions 33234H GLD_MSR_SMI Bit Descriptions (Continued) Bit Name Description 40 SEQIOR_SMI Sequencer Register Read SMI. Reading a 1 indicates that one or more of the VGA’s Sequencer registers has been read; writing a 1 to this bit clears it. 39 SEQIOW_SMI Sequencer Register Write SMI. Reading a 1 indicates that one or more of the VGA’s Sequencer registers has been written; writing a 1 to this bit clears it. 38 CRTCIOR_SMI CRTC Register Read SMI.
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33234H Display Controller Register Descriptions GLD_MSR_SMI Bit Descriptions (Continued) Bit Name Description 9 GFXIOW_MSK Graphics Controller Register Write SMI. When set to 1, disables generation of the SMI that indicates that one or more of the VGA’s Graphics Controller registers has been written. 8 SEQIOR_MSK Sequencer Register Read SMI. When set to 1, disables generation of the SMI that indicates that one or more of the VGA’s Sequencer registers has been read.
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33234H Display Controller Register Descriptions GLD_MSR_ERROR Bit Descriptions Bit Name Description 63:38 RSVD Reserved. Set to 0. 37 CWD_CHECK_ERR Control Word Check Error. Reading a 1 indicates that an invalid control word was read from the Display FIFO, which is indicative of a FIFO underrun. Writing a 1 to this bit clears it. 36 SYNCBUF_ERR Synchronizer Buffer Error. Reading a 1 indicates that the display pipe attempted to read the synchronizer buffer while it was invalid.
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33234H Display Controller Register Descriptions 6.6.1.5 GLD Power Management MSR (GLD_MSR_PM) MSR Address 80002004h Type R/W Reset Value 00000000_00000015h GLD_MSR_PM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 7 6 5 4 3 2 1 0 GLCLK_PMODE 8 DCLK_PMODE RSVD 9 VGA_GLCLK_PMODE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 GLD_MSR_PM Bit Descriptions Bit Name Description 63:6 RSVD Reserved. Set to 0.
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33234H Display Controller Register Descriptions 6.6.2 Display Controller Specific MSRs 6.6.2.1 SPARE MSR MSR Address 80000011h Type R/W Reset Value 00000000_00000000h SPARE_MSR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 9 8 7 6 5 4 DISABLE_VFIFO_WM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 3 2 1 0 RSVD SPARE_MSR Bit Descriptions Bit Name Description 63:7 RSVD Reserved.
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33234H 6.6.3 Display Controller Register Descriptions Configuration and Status Registers All DC registers are DWORD accessible only. 6.6.3.1 DC Unlock (DC_UNLOCK) DC Memory Offset 000h Type R/W Reset Value 00000000h This register is provided to lock the most critical memory-mapped DC registers to prevent unwanted modification (write operations). Read operations are always allowed.
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33234H Display Controller Register Descriptions DC_UNLOCK Bit Descriptions Bit Name Description 31:16 RSVD Reserved. 15:0 DC_UNLOCK Unlock Code. This register must be written with the value 4758h in order to write to the protected registers.
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33234H Display Controller Register Descriptions 6.6.3.2 DC General Configuration (DC_GENERAL_CFG) DC Memory Offset 004h Type R/W Reset Value 00000000h This register contains general control bits for the DC. Unless otherwise noted in the bit descriptions table, settings written to this register do not take effect until the start of the following frame or interlaced field.
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Display Controller Register Descriptions 33234H DC_GENERAL_CFG Bit Descriptions (Continued) Bit Name Description 24 SIGE Signature Enable. Effective immediately. 0: CRC Signature is reset to 000001h and held (no capture). 1: CRC Logic captures the pixel data signature with each pixel clock beginning with the next leading edge of vertical blank.
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33234H Display Controller Register Descriptions DC_GENERAL_CFG Bit Descriptions (Continued) Bit 11:8 7 Name Description DFHPSL Display-FIFO High Priority Start Level. This field specifies the depth of the display FIFO (in multiples of 256 bytes) at which a high-priority request is sent to the memory controller to fill up the FIFO. The value is dependent upon display mode. This field should always be non-zero and should be less than the high-priority end level.
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33234H Display Controller Register Descriptions 6.6.3.3 DC Display Configuration (DC_DISPLAY_CFG) DC Memory Offset 008h Type R/W Reset Value 00000000h This register contains configuration bits for controlling the various display functions of the DC. Unless otherwise noted, settings written to this register do not take effect until the start of the following frame or interlaced field.
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33234H Display Controller Register Descriptions DC_DISPLAY_CFG Bit Descriptions (Continued) Bit Name Description 9:8 DISP_MODE Display Mode. Bits per pixel. 00: 8-bpp (also used in VGA emulation) 01: 16-bpp 10: 24-bpp (RGB 8:8:8) 11: 32-bpp 7 RSVD Reserved. 6 TRUP Timing Register Update. Effective immediately. 0: Prevent update of working timing registers.
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33234H Display Controller Register Descriptions 6.6.3.4 DC Arbitration Configuration (DC_ARB_CFG) DC Memory Offset 00Ch Type R/W Reset Value 00000000h This register contains configuration bits for controlling the priority level of GLIU requests by the DC. It allows high priority to be enabled under several conditions (see bits [8:1]). These conditions are ORed with other sources of high-priority, including the FIFO watermark mechanisms. Settings written to this register take effect immediately.
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33234H Display Controller Register Descriptions DC_ARB_CFG Bit Descriptions (Continued) Bit Name Description 3 HPEN_2LB_INV High Priority Enable when Any Two Line Buffers Invalid. This bit enables the DC to arbitrate at high priority if the scaler filter is enabled and any two of the three line buffers that feed this filter are invalid. (The state of this bit is ignored if the scaler filter is disabled.) 2 HPEN_3LB_INV High Priority Enable when Any Three Line Buffers Invalid.
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33234H Display Controller Register Descriptions 6.6.4 Memory Organization Registers The graphics memory region is up to 16 MB in size. The graphics memory is made up of the normal uncompressed frame buffer, compressed display buffer, cursor buffer, cursor color buffer (for 16-bit color cursor), and video buffer(s). Each buffer begins at a programmable offset within the graphics memory region. The various memory buffers are arranged so as to efficiently pack the data within the graphics memory region.
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33234H Display Controller Register Descriptions 6.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET) DC Memory Offset 014h Type R/W Reset Value xxxxxxxxh This register specifies the offset at which the compressed display buffer starts. Settings written to this register do not take effect until the start of the following frame or interlaced field.
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33234H Display Controller Register Descriptions 6.6.4.4 DC Video Y Buffer Start Address Offset (DC_VID_Y_ST_OFFSET) DC Memory Offset 020h Type R/W Reset Value xxxxxxxxh This register specifies the offset at which the video Y (YUV 4:2:0) or YUV (YUV 4:2:2) buffer starts. The upper 4 bits of this register are for the field count mechanism.
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33234H Display Controller Register Descriptions DC_VID_U_ST_OFFSET Bit Descriptions Bit Name Description 31:28 FRAME_COUNT Frame Count. When reading this register, this field indicates the current frame count, as determined by counting rising edges of VIP VSYNC. This value is reset to 0 when VIP_VSYNC occurs and FRAME_CNT >= FRAME_LIMIT. It can also be written to provide a mechanism for software to synchronize activities between the VIP and the Display Controller.
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33234H Display Controller Register Descriptions DC_DV_TOP Bit Descriptions Bit Name Description 31:24 RSVD Reserved. These bits should be programmed to zero. 23:10 DV_TOP_ADDR Dirty/Valid Region Top Address. When enabled via bit 0 (DV_TOP_EN), this field indicates the size of the region to be watched for frame buffer accesses. When writes to this region occur and the compression logic is in frame-dirty mode, the frame is marked as dirty.
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33234H Display Controller Register Descriptions 6.6.4.9 DC Graphics Pitch (DC_GFX_PITCH) DC Memory Offset 034h Type R/W Reset Value xxxxxxxxh This register stores the pitch for the graphics display buffers. DC_GFX_PITCH Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CB_PITCH 8 7 6 5 4 3 2 1 0 FB_PITCH DC_GFX_PITCH Bit Descriptions Bit Name Description 31:16 CB_PITCH Compressed Display Buffer Pitch.
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33234H Display Controller Register Descriptions 6.6.5 Timing Registers The DC timing registers control the generation of sync, blanking, and active display regions. These registers are generally programmed by the BIOS from an INT 10h call or by the extended mode driver from a display timing file. Example: To display a 1024x768 graphics (frame buffer) image on a 720x483/59.94 television.
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33234H Display Controller Register Descriptions 6.6.5.1 DC Horizontal and Total Timing (DC_H_ACTIVE_TIMING) DC Memory Offset 040h Type R/W Reset Value xxxxxxxxh This register contains horizontal active and total timing information. DC_H_ACTIVE_TIMING Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD H_TOTAL 9 RSVD 8 7 6 5 4 3 2 1 0 H_ACTIVE DC_H_ACTIVE_TIMING Bit Descriptions Bit Name Description 31:28 RSVD Reserved.
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33234H Display Controller Register Descriptions 6.6.5.2 DC CRT Horizontal Blanking Timing (DC_H_BLANK_TIMING) DC Memory Offset 044h Type R/W Reset Value xxxxxxxxh This register contains CRT horizontal blank timing information. Note: A minimum of 32 pixel clocks is required for the horizontal blanking portion of a line in order for the timing generator to function correctly.
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33234H Display Controller Register Descriptions DC_H_SYNC_TIMING Bit Descriptions Bit Name Description 15:12 RSVD Reserved. These bits should be programmed to zero. 11:0 H_SYNC_ST Horizontal Sync Start. This field represents the pixel clock count at which the CRT horizontal sync signal becomes active minus 1. Unlike previous versions of the DC, this field can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity.
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33234H Display Controller Register Descriptions 6.6.5.5 DC CRT Vertical Blank Timing (DC_V_BLANK_TIMING) DC Memory Offset 054h Type R/W Reset Value xxxxxxxxh This register contains vertical blank timing information. All values are specified in lines. For interlaced display, no border is supported, so blank timing is implied by the total/active timing.
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34H Display Controller Register Descriptions 6.6.5.7 DC Frame Buffer Active Region Register (DC_FB_ACTIVE) DC Memory Offset 05Ch Type R/W Reset Value xxxxxxxxh DC_FB_ACTIVE Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FB_H_ACTIVE 9 8 7 6 5 4 3 2 1 0 FB_V_ACTIVE DC_FB_ACTIVE Bit Descriptions Bit 31:16 Name Description FB_H_ACTIVE Horizontal Frame Buffer Active End. This field is used only when graphics scaling is enabled.
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33234H Display Controller Register Descriptions DC_CURSOR_X Bit Descriptions Bit Name Description 16:11 X_OFFSET X Offset. This field represents the X pixel offset within the 64x64 cursor pattern at which the displayed portion of the cursor is to begin.
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33234H Display Controller Register Descriptions DC_LINE_CNT/STATUS Register Map SIGC VFLIP FLIP RSVD VSA VNA DNA V_LINE_CNT EVEN_FIELD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSVD 6 5 4 3 2 1 0 DOT_LINE_CNT DC_LINE_CNT/STATUS Bit Descriptions Bit Name Description 31 DNA Display Not Active. 0: Display active. 1: Display not active (i.e., blanking or border). 30 VNA Vertical Not Active. 0: Vertical display active.
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33234H Display Controller Register Descriptions 6.6.7 Palette Access FIFO Diagnostic Registers The Palette Access registers are used for accessing the internal palette RAM and extensions. In addition to the standard 256 entries for color translation, the palette has extensions for cursor colors and overscan (border) color. The diagnostics registers enable testability of the display FIFO and compression FIFO. 6.6.7.
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33234H Display Controller Register Descriptions 6.6.7.2 DC Palette Data (DC_PAL_DATA) DC Memory Offset 074h Type R/W Reset Value xxxxxxxxh This register contains the data for a palette access cycle. When a read or write to the palette RAM occurs, the previous output value is held for one additional Dot clock period. This effect should go unnoticed and will provide for sparkle-free updates.
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33234H Display Controller Register Descriptions 6.6.7.4 DC Compression FIFO Diagnostic (DC_CFIFO_DIAG) DC Memory Offset 07Ch Type R/W Reset Value xxxxxxxxh This register is provided to enable testability of the compressed line buffer (FIFO) RAM. Before it is accessed, the DIAG bit should be set high (DC Memory Offset 004h[28] = 1) and the DFLE bit should be set low (DC Memory Offset 004h[0] = 0).
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33234H 6.6.8 Display Controller Register Descriptions Video Downscaling 6.6.8.1 DC Video Downscaling Delta (DC_VID_DS_DELTA) DC Memory Offset 080h Type R/W Reset Value 00000000h This register is provided to allow downscaling of the video overlay image by selective skipping of source lines.
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33234H Display Controller Register Descriptions 6.6.9 GLIU Control Registers 6.6.9.1 DC GLIU0 Memory Offset (DC_GLIU0_MEM_OFFSET) DC Memory Offset 084h Type R/W Reset Value 00000000h This register is used to set a base address for the graphics memory region. The value in this register is added to all outgoing memory addresses. Because the base address must be aligned to a 16 MB region, only bits [31:24] of this register are used.
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33234H Display Controller Register Descriptions DV_CTL Bit Descriptions (Continued) Bit 11:10 Name Description DV_LINE_SIZE DV Line Size. This field determines how many bytes of frame buffer space correspond to an entry in the DV RAM. The value selected by this field must be greater than or equal to the FB_LINE_SIZE, as programmed in the DC_LINE_SIZE register (DC Memory Offset 030h[9:0]).
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33234H Display Controller Register Descriptions 6.6.10 Graphics Scaling Control Registers 6.6.10.1 DC Graphics Filter Scale (DC_GFX_SCALE) DC Memory Offset 090h Type R/W Reset Value 40004000h DC_GFX_SCALE Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 V_SCALE 9 8 7 6 5 4 3 2 1 0 H_SCALE DC_GFX_SCALE Bit Descriptions Bit 31:16 Name Description V_SCALE Vertical Filter Scale.
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33234H Display Controller Register Descriptions 6.6.10.2 DC IRQ/Filter Control (DC_IRQ_FILT_CTL) DC Memory Offset 094h Type R/W Reset Value 00000000h DC_IRQ_FILT_CTL Register Map 9 8 INTL_EN 7 6 5 4 3 2 1 0 FILT_ADDR H_FILT_SEL FILT_ENA RSVD RSVD RSVD ALPHA_FILT_ENA LINE_COUNT RSVD INTERLACE_ADDRESSING RSVD LINEBUF_SEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DC_IRQ_FILT_CTL Bit Descriptions Bit Name Description 31 RSVD Reserved.
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33234H Display Controller Register Descriptions DC_IRQ_FILT_CTL Bit Descriptions (Continued) Bit Name Description 11 INTL_EN Interlace Enable. Settings written to this field will not take effect until the start of the following frame or interlaced field. Setting this bit to 1 configures the output to interlaced mode. In this mode, the vertical timings are based on the even timing registers for every other field. This bit must be set if the flicker filter or address interlacing is enabled.
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33234H Display Controller Register Descriptions 6.6.10.4 DC Filter Coefficient Data Register 2 (DC_FILT_COEFF2) DC Memory Offset 09Ch Type R/W Reset Value xxxxxxxxh Any read or write of this register causes a read or write of the horizontal or filter coefficient RAM. If this occurs while the display is active, improper filtering of an output pixel can occur, which may cause temporary visual artifacts (speckling).
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33234H Display Controller Register Descriptions DC_VBI_EVEN_CTL Bit Descriptions (Continued) Bit Name Description 28 VBI_ENA VBI Enable. Setting this bit to 1 enables VBI (Vertical Blank Interrupt) data. This is a data stream that is placed in the off-screen region at the start of each field. This data is passed through the graphics output path, but is not filtered or modified in any way. VBI_EVEN_ OFFSET VBI Even Address Offset. Indicates the starting offset for VBI data for even fields.
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33234H Display Controller Register Descriptions 6.6.11.4 DC VBI Odd Line Enable (DC_VBI_LN_ODD) DC Memory Offset 0ACh Type R/W Reset Value xxxxxxxxh Settings written to this register do not take effect until the start of the following frame or interlaced field.
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33234H Display Controller Register Descriptions 6.6.11.6 DC VBI Pitch and Size (DC_VBI_PITCH) DC Memory Offset 0B4h Type R/W Reset Value xxxxxxxxh DC_VBI_PITCH Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 VBI_Size 8 7 6 5 4 3 2 1 0 VBI_Pitch DC_VBI_PITCH Bit Descriptions Bit Name Description 31:26 RSVD Reserved. Set to 0. 25:16 VBI_SIZE VBI Data Size.
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33234H Display Controller Register Descriptions 6.6.12.2 DC Color Key Mask (DC_CLR_KEY_MASK) DC Memory Offset 0BCh Type R/W Reset Value 00xxxxxxh DC_CLR_KEY_MASK Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 CLR_KEY_MASK DC_CLR_KEY_MASK Bit Descriptions Bit Name Description 31:24 RSVD Reserved. Set to 0. 23:0 CLR_KEY_ MASK Color Key Mask.
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33234H Display Controller Register Descriptions DC_CLR_KEY_Y Bit Descriptions Bit Name Description 31:27 RSVD Reserved. Set to 0. 26:16 CLR_KEY_Y_ END Color Key Vertical End. This field represents the vertical end position of the color key region minus 1. This represents the first line past the end of the color key region. 15:11 RSVD Reserved. Set to 0. 10:0 CLR_KEY_Y_ START Color Key Vertical Start. This field represents the vertical start position of the color key region minus 1.
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33234H 6.6.13 Display Controller Register Descriptions Interrupt and GenLock Registers 6.6.13.1 DC GenLock Control (DC_GENLK_CTL) DC Memory Offset 0D4h Type R/W Reset Value xxxxxxxxh Settings written to this register do not take effect until the start of the frame or interlaced field after the timing register update bit (DC Memory Offset 008h[6]) is set.
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33234H Display Controller Register Descriptions DC_GENLK_CTL Bit Descriptions (Continued) Bit Name Description 20 VIP_VSYNC_ WAIT (RO) VIP VSYNC Wait (Read Only). If set to 1 this status bit indicates that the DC has completed a field or frame and is waiting for the VIP’s VSYNC to go active before beginning another frame. Typically, this will occur only if the VIP_VIDEO_OK (bit 23) input is active or the GENLOCK_TO _EN (bit 19) is inactive. 19 GENLK_TO_EN GenLock Time Out Enable.
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33234H Display Controller Register Descriptions 6.6.14.2 DC Even Field Video U Start Address Offset (DC_VID_EVEN_U_ST_OFFSET) DC Memory Offset 0DCh Type R/W Reset Value xxxxxxxxh Settings written to this register do not take effect until the start of the next even interlaced field.
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33234H Display Controller Register Descriptions 6.6.15 Even Field Vertical Timing Registers 6.6.15.1 DC Vertical and Total Timing for Even Fields (DC_V_ACTIVE_EVEN_TIMING) DC Memory Offset 0E4h Type R/W Reset Value xxxxxxxxh This register contains vertical active and total timing information. These parameters pertain ONLY to even fields in interlaced display modes (The DC_V_ACTIVE_TIMING register (DC Memory Offset 050h) will take effect for odd fields in interlaced display modes.
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33234H Display Controller Register Descriptions 6.6.15.2 DC CRT Vertical Blank Timing for Even Fields (DC_V_BLANK_EVEN_TIMING) DC Memory Offset 0E8h Type R/W Reset Value xxxxxxxxh This register contains vertical blank timing information. All values are specified in lines. This register is used ONLY for even fields in interlaced display modes.
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33234H Display Controller Register Descriptions 6.6.16 VGA Block Configuration Registers 6.6.16.1 VGA Configuration (VGA_CONFIG) DC Memory Offset 100h Type R/W Reset Value 00000000h This register controls palette write operations. VGA_CONFIG Register Map 9 8 7 6 5 4 3 2 1 0 WPPAL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD VGA_CONFIG Bit Descriptions Bit Name Description 31:1 RSVD Reserved. Set to 0. WPPAL Write Protect Palette.
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33234H Display Controller Register Descriptions VGA_STATUS Bit Descriptions (Continued) Bit Name Description 2 VBLANK_SMI VBLANK SMI. If = 1, an SMI was generated due to leading edge vertical blank. 1 ISR0_SMI Input Status Register 0 SMI. If = 1, an SMI was generated from an I/O IN to Input Status Register 0. 0 MISC_SMI Miscellaneous Output Register SMI. If = 1, an SMI was generated from an I/O OUT to the Miscellaneous Output Register. 6.6.17 VGA Block Standard Registers 6.6.17.
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Display Controller Register Descriptions 33234H 6.6.17.2 VGA Input Status Register 0 Read Address 3C2h Write Address -Type R/W Reset Value 00h VGA Input Status Register 0 Bit Descriptions Bit Name Description 7 RSVD Not Implemented. (CRTC Interrupt Pending) 6:5 RSVD Reserved. 4 RSVD Not Implemented. (Display Sense) 3:0 RSVD Reserved. 6.6.17.
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33234H 6.6.18 Display Controller Register Descriptions VGA Sequencer Registers The Sequencer registers are accessed by writing an index value to the Sequencer Index register (3C4h) and reading or writing the register using the Sequencer Data register (3C5h). Table 6-51.
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Display Controller Register Descriptions 33234H 6.6.18.4 VGA Clocking Mode Index 01h Type R/W Reset Value 02h VGA Clocking Mode Register Bit Descriptions Bit Name Description 7:6 RSVD Reserved. 5 SCREEN_OFF Screen Off. Setting this bit to a 1 blanks the screen while maintaining the HSYNC and VSYNC signals. This is intended to allow the CPU full access to the memory bandwidth. This bit must be 0 for the display image to be visible. 4 RSVD Not Supported.
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33234H Display Controller Register Descriptions 6.6.18.6 VGA Character Map Select Index 03h Type R/W Reset Value xxh Character Map A (bits [5,3:2]) and Character Map B (bits [4,1:0]) determine which font tables are used when displaying a character in text mode. When bit 3 of the character's attribute = 1, Character Map A is used; when bit 3 of the character's attribute = 0, Character Map B is used. The font tables are stored in the 64 KB in map 2. There are eight font tables.
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33234H Display Controller Register Descriptions 6.6.19 VGA CRT Controller Registers The CRTC registers are accessed by writing an index value to the CRTC Index register (3B4h or 3D4h) and reading or writing the register using the CRTC Data register (3B5h or 3D5h). See the description of the I/O Address Select bit in the Miscellaneous Output register (Section 6.6.17.1 on page 356) for more information on the I/O address of the CRTC registers.
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33234H Display Controller Register Descriptions Table 6-54.
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33234H Display Controller Register Descriptions 6.6.19.2 CRTC Data Data Address 3B5h or 3D5h Type R/W Reset Value 00h CRTC Data Register Bit Descriptions Bit Name Description 7 RSVD Reserved. 6:0 DATA Data. 6.6.19.3 Horizontal Total Index 00h Type R/W Reset Value 00h Horizontal Total Register Bit Descriptions Bit Name Description 7:0 H_TOTAL Horizontal Total. This value specifies the number of character clocks per horizontal scan line minus 5. It determines the horizontal line rate/period.
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33234H Display Controller Register Descriptions 6.6.19.6 Horizontal Blank End Index 03h Type R/W Reset Value 00h Horizontal Blank End Register Bit Descriptions Bit Name Description 7 RSVD Reserved. Set to 1. 6:5 DISPEN_SKEW Display Enable Skew Control. This value is a binary encoded value that specifies how many character clocks to skew the horizontal display enable signal by (0 character clocks - 3 character clocks) before it is sent to the attribute controller.
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33234H Display Controller Register Descriptions 6.6.19.9 Vertical Total Index 06h Type R/W Reset Value 00h Vertical Total Register Bit Descriptions Bit Name Description 7:0 V_TOTAL[7:0] Vertical Total Register Bits [7:0]. This is the low eight bits of a value that specifies the total number of scan lines on the screen minus 2. This value includes the blanking area and determines the vertical refresh rate. The high two bits of this value are in the Overflow register (Index 07h[5,1]). 6.6.19.
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33234H Display Controller Register Descriptions Preset Row Scan Register Bit Descriptions Bit Name Description 6:5 BYPE_PAN Byte Panning. This value causes the pixel data stream to be fetched zero, one, two, or three character positions early for use with pel panning in the attribute controller. This field is used when the video serializers are chained together (by two or by four). 4:0 ROW_SCAN Starting Row Scan.
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33234H Display Controller Register Descriptions 6.6.19.14 Cursor End Index 0Bh Type R/W Reset Value 00h Cursor End Register Bit Descriptions Bit Name Description 7 RSVD Reserved. 6:5 CURS_SKEW Cursor Skew. This field allows the cursor to be skewed by zero, one, two, or three character positions to the right. 4:0 CURS_END Cursor End. This field specifies the last scan line in the character box where the cursor is displayed. See CURS_ST bit descriptions (Index 0Ah[4:0]) for more information. 6.
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33234H Display Controller Register Descriptions 6.6.19.18 Cursor Location Low Index 0Fh Type R/W Reset Value 00h Cursor Location Low Register Bit Descriptions Bit Name Description 7:0 CURS_LOW Cursor Location Register Bits [7:0]. Together with the register (CURS_HI, Index 0Eh[7:0]), this value specifies the frame buffer address where the cursor is displayed in text mode. The cursor will appear at the character whose memory address corresponds to this value. 6.6.19.
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33234H Display Controller Register Descriptions 6.6.19.21 Vertical Display Enable End Index 12h Type R/W Reset Value 00h Vertical Display Enable End Register Bit Descriptions Bit Name Description 7:0 V_DISP_EN_ END Vertical Display Enable End Register Bits [7:0]. This is a 10-bit value that specifies the scan line where the vertical display enable signal goes inactive. It represents the number of active scan lines minus 1. Bits 9 and 8 of this value are in the Overflow register (Index 07h[6,1]). 6.
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33234H Display Controller Register Descriptions 6.6.19.24 Vertical Blank Start Index 15h Type R/W Reset Value 00h Vertical Blank Start Register Bit Descriptions Bit Name Description 7:0 V_BL_ST Vertical Blank Start Register Bits [7:0]. This is the low eight bits of a value that specifies the starting scan line of the vertical blank signal. This is a 10-bit value. Bit 8 is in the Overflow register (Index 07h[3]) and bit 9 is in the Maximum Scan Line register (Index 09h[5]). 6.6.19.
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33234H Display Controller Register Descriptions CRTC Mode Control Register Bit Descriptions (Continued) Bit Name Description 1 SL_RSCBT Select Row Scan Bit. This bit determines which CRTC signal appears on the MA14 address bit sent to the frame buffer memory. If this bit is a 0, bit 1 of the Row Scan counter appears on MA14. If this bit is a 1, then CRTC address counter bit 14, 13, or 12 appears on MA14. See Table 6-55 on page 371 for more information. 0 SL_A13 Select A13.
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33234H Display Controller Register Descriptions 6.6.19.27 Line Compare Index 18h Type R/W Reset Value 00h Line Compare Register Bit Descriptions Bit Name Description 7:0 LINE_COMP[7:0] Line Compare Register Bits [7:0]. This value specifies the low eight bits of a compare value that represents the scan line where the CRTC frame buffer address counter is reset to 0.
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33234H Display Controller Register Descriptions 6.6.19.30 Attribute Index State Index 26h Type RO Reset Value xxh Attribute Index State Register Bit Descriptions Bit Name Description 7:6 RSVD Reserved. 5:0 ATT_IN_VA Attribute Index Value. This read only value indicates the value of Attribute Index register bits [5:0] (Index 3C0h). 6.6.
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33234H Display Controller Register Descriptions 6.6.20.2 VGA Graphics Controller Data Data Address 3CFh Type R/W Reset Value xxh VGA Graphics Controller Data Register Bit Descriptions Bit Name Description 7:4 RSVD Reserved. 3:0 DATA Data. 6.6.20.3 VGA Set/Reset Index 00h Type R/W Reset Value xxh Bits [3:0] allow bits in their respective maps to be set or reset through write modes 0 or 3. See Section 6.5.5.3 "Write Modes" on page 290 for more information.
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Display Controller Register Descriptions 33234H 6.6.20.5 VGA Color Compare Index 02h Type R/W Reset Value xxh Bits [3:0] specify a compare value that allows the CPU to compare pixels in planar modes. Read mode 1 performs a comparison based on these bits combined with the Color Don’t Care bits. Data returned will contain a 1 in each one of the eight pixel positions where a color match is found. See the description of read modes (Section 6.5.5.4 on page 291) for more information.
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33234H Display Controller Register Descriptions 6.6.20.7 VGA Read Map Select Index 04h Type R/W Reset Value xxh VGA Read Map Select Register Bit Descriptions Bit Name Description 7:2 RSVD Reserved. 1:0 R_MP_SL Read Map Select. This field specifies which map CPU read data is taken from in read mode 0. In Odd/Even modes (specified by the Odd/Even bit in the Graphics Mode register, Index 05h[4]) bit 1 of this field specifies which pair of maps returns data.
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Display Controller Register Descriptions 33234H VGA Graphics Mode Register Bit Descriptions Bit Name Description 1:0 WR_MD Write Mode. This field specifies how CPU data is written to the frame buffer. Note that the Write Operation field in the VGA Data Rotate register (Index 03h[4:3]) specifies how CPU data is combined with data in the data latches for write modes 0, 2, and 3. 00: Write Mode 0: CPU data is rotated by the count in the VGA Data Rotate register.
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33234H Display Controller Register Descriptions 6.6.20.10 VGA Color Don’t Care Index 07h Type R/W Reset Value xxh VGA Color Don’t Care Register Bit Descriptions Bit Name Description 7:4 RSVD Reserved. 3 CM_PR3 Compare Map 3. This bit enables (bit = 1) or excludes (bit = 0) map 3 from participating in a color compare operation. 2 CM_PR2 Compare Map 2. This bit enables (bit = 1) or excludes (bit = 0) map 2 from participating in a color compare operation. 1 CM_PR1 Compare Map 1.
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33234H Display Controller Register Descriptions 6.6.21.1 Attribute Controller Index/Data Index Address 3C0h Data Address 3C1h (R) 3C0h (W) Type R/W Reset Value xxh The attribute controller registers do not have a separate address for writing index and data information. Instead, an internal flip-flop alternates between index and data registers. Reading Input Status Register 1 (3BAh or 3DAh) clears the flip-flop to the index state.
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33234H Display Controller Register Descriptions 6.6.21.3 Attribute Mode Control Index 10h Type R/W Reset Value xxh Attribute Mode Control Register Bit Descriptions Bit Name Description 7 P5:4_SEL P5:4 Select. When this bit is a 1, bits [5:4] of the 8-bit VGA pixel value are taken from bits [1:0] of the Color Select register (Index 14h). When a 0, bits [5:4] of the pixel are taken from bits [5:4] of the EGA palette output. 6 PEL_W Pel Width.
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33234H Display Controller Register Descriptions 6.6.21.5 Color Plane Enable Index 12h Type R/W Reset Value xxh Color Plane Enable Register Bit Descriptions Bit Name Description 7:4 RSVD Reserved. 3 EN_CO_PN3 Enable Color Plane 3. This bit enables color plane 3. It is ANDed with it corresponding pixel bit and the resulting 4-bit value is used as the address into the EGA palette. 2 EN_CO_PN2 Enable Color Plane 2. This bit enables color plane 2.
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33234H Display Controller Register Descriptions 6.6.21.7 Color Select Index 14h Type R/W Reset Value xxh Color Select Register Bit Descriptions Bit Name Description 7:4 RSVD Reserved. 3:2 P[7:6] P7 and P6. These bits are used to provide the upper two bits of the 8-bit pixel value sent to the video DAC in all modes except the 256 color mode (mode 13h). 1:0 P[5:4] P5 and P4.
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Display Controller Register Descriptions 33234H 6.6.22.1 Video DAC Palette Address Read Address 3C8h Write Address 3C7h (Palette Read Mode) 3C8h (Palette Write Mode) Type RO Reset Value 00h Video DAC Palette Address Register Bit Descriptions Bit Name Description 7:0 ADDR Palette Address. 6.6.22.2 Video DAC State Read Address 3C7h Write Address -Type RO Reset Value 00h Video DAC State Register Bit Descriptions Bit Name Description 7:2 RSVD Reserved. 1:0 DAC_ST DAC State.
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33234H Display Controller Register Descriptions 6.6.22.4 Video DAC Palette Mask Read Address 3C6h Write Address 3C6h Type R/W Reset Value 00h Video DAC Palette Mask Register Bit Descriptions Bit Name Description 7:0 PAL_MSK Palette Mask. These bits enable their respective color bits between the final VGA 8-bit pixel output and the DAC palette. The bits are ANDed with the incoming VGA pixel value and the result used to address the palette RAM. 6.6.
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Display Controller Register Descriptions 33234H 6.6.23.1 ExtendedRegisterLock CRTC Index 030h Type R/W Reset Value FFh ExtendedRegisterLock Register Bit Descriptions Bit Name Description 7:0 LOCK Lock. A value of 4Ch unlocks the extended registers. Any other value locks the extended registers so they are read only. If the extended registers are currently locked, a read to this register will return FFh. If they are unlocked, a read will return 0. 6.6.23.
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33234H Display Controller Register Descriptions 6.6.23.4 WriteMemoryAperture CRTC Index 047h Type R/W Reset Value 00h WriteMemoryAperture Register Bit Descriptions Bit Name Description 7:0 WR_BASE WriteBase. Offset added to the graphics memory base to specify where VGA write operations start. This value provides DWORD address bits [21:14] when mapping host VGA writes to graphics memory. This allows the VGA base address to start on any 64 KB boundary within the 8 MB of graphics memory. 6.6.23.
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Display Controller Register Descriptions 33234H 6.6.23.7 BlinkCounter CRTC Index 061h Type RO Reset Value 00h This register is for simulation and test only. BlinkCounter Register Bit Descriptions Bit Name Description 7:5 RSVD Reserved. 4:0 BLNK_CNT Blink Count. These bits provide a real-time blink counter value. This register is not synchronized to the system clock domain. 6.6.23.
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33234H 6.7 Video Processor Video Processor The Video Processor (VP) module provides a high-performance, low-power CRT/TFT display or video output interface. There are three main functions contained within the VP: the Video Processor, the TFT controller, and the video output port (VOP). The scaling, filtering, and color space conversion algorithms implemented in the VP are of much higher quality than those used in software-only video playback systems.
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33234H Video Processor Video Processor Module 3 Display Controller Video Data Controller 2 Video Data 16 Video Processor Video Data Interface (YUV) Graphics Data Video Formatter Delay X and Y Scaler 24 3 Control Registers Interface Mixer/Blender (Overly with Alpha Blending, CSC and Gamma RAM) Graphics Data Interface (RGB) VP YUV Video Output + Cntl Port Output Devices 3 Dot Clock 27 Companion Device Bypass fmt_sel 27 VP RGB + Cntl 16 Output Format (MUX) Pixel Cntl 24 3 CRT DAC (3x8
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33234H Video Processor 6.7.2 Functional Description The VP receives the input video stream in either YUV (4:2:2 or 4:2:0) or RGB (5:6:5) format. The VP has an integrated color space converter to convert YUV data to RGB data. The video clock must always be active (regardless of the source of video input). Either graphics, or graphics and video mixed (via colorkeying or alpha-blending) can be displayed. Mixing can be performed in either the RGB or YUV domain.
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33234H Video Processor 6.7.2.1 Video Formatter The Video Processor module accepts video data at a rate asynchronous to the GLIU clock rate. The byte order of video input data can be configured using the VID_FMT bits in the Video Configuration register (VP Memory Offset 000h[3:2]). Four subformats can be selected via the VID_FMT bits (VP Memory Offset 000h[3:2]): Video input data can be in YUV 4:2:2, YUV 4:2:0, or RGB 5:6:5 format.
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33234H Video Processor 6.7.2.3 Horizontal Downscaling The Video Processor module supports horizontal downscaling (see Figure 6-25). The downscaler can be implemented in the Video Processor module to shrink the video window by a factor of up to 8:1, in one-pixel increments. The Downscaler Factor Select (m) is programmed in the Video Downscaler Control register (VP Memory Offset 078h[4:1]). If bit 0 (DCF) of this register is set to 0, the downscaler logic is bypassed.
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33234H Video Processor 6.7.3 X and Y Upscaler After the video data has been buffered, the upscaling algorithm is applied. The Video Processor module employs a Digital Differential Analyzer-style (DDA) algorithm for both horizontal and vertical upscaling. The scaling parameters are programmed via the Video Scale register (VP Memory Offset 020h). The scalers support up to 8x scale factors both horizontally and vertically.
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33234H 6.7.5 Video Overlay Video data is mixed with graphics data according to the video window position. The video window position is programmable via the Video X Position (VP Memory Offset 010h) and Video Y Position (VP Memory Offset 018h) registers.
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33234H Video Processor Video YUV Video HD/SD YUV_CSC_EN YUV CSC_VIDEO to YUV YUV CSC 0 0 1 YUV 1 to RGB RGB CSC 1 0 Current Pixel Location bypass_stream GV_PAL_BP Palette RAM palette_stream 0 Color Key and Blending Logic 1 Cursor_Color_Key CUR_COLOR_MASK RGB/YUV Compare 1 Compare VID_CLR_KEY VID_CLR_MASK 31:24 0 Alpha Color Registers and Cursor Color Values SAT_Scale_EN 8 SAT_Scale Graphics VG_CK VSYNC RGB to HSV Saturation Control HSV to RGB RGB CSC HD/SD 0 1 CSC_GFX RGB to YUV CSC
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33234H Video Processor Notes: Start Use selected cursor color for pixel. Cursor color key matches graphics value? Yes No Use graphics value for this pixel. 1) VG_CK: Video/Graphics color key select (VP Memory Offset 008h[20]). Selects whether graphic data is used for color keying or video data is used for chroma keying. 2) GFX_INS_VIDEO: Graphics inside Video (VP Memory Offset 098h[8]). Graphics inside video enable.
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33234H Video Processor Table 6-60 represents the same logic that is displayed in Figure 6-28 on page 396. Table 6-60.
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33234H 6.7.6 Video Processor Video Output Port 6.7.6.2 6.7.6.1 Functional Overview The Video Output Port (VOP) receives YUV 4:4:4 encoded data from the VP and formats the data into a video-stream that is BT.656) or BT.601 compliant. Output from the VOP goes to either a VIP or a TV encoder. The VOP must be BT.656/BT.601 compliant since its output may go directly (or indirectly) to a display. Slave Interface Data from Blender VOP Registers 4:4:4 to 4:2:2 Converter Supported Features • VIP 2.
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33234H Video Processor 6.7.6.3 HBLANK and VBLANK Signals HBLANK and VBLANK signals are different from HSYNC and VSYNC. The HSYNC and VSYNC signals are only active for a portion of the blanking time, while the HBLANK and VBLANK signals are active through the entire time. HBLANK is a function of horizontal pixel position, while VBLANK is a function of the vertical line number and the horizontal pixel position. Figures 6-30 to 6-34 show the formation of these signals using a 525-line NTSC video window.
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33234H Pixel Position Video Processor 720 721 858 244 Line Number 001 245 HBLANK VBLANK Figure 6-32. HBLANK and VBLANK for Lines 263, 525 Pixel Position 720 721 858 L# Line Number 001 L# + 1 HBLANK VBLANK Figure 6-33. HBLANK and VBLANK for Lines 1-18, 264-281 Pixel Position Line Number 720 721 294 858 001 001 HBLANK VBLANK Figure 6-34.
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33234H Video Processor 6.7.6.4 Interface to Video Processor The output from the Video Processor is connected via a 24-bit bus. Bytes on this bus are aligned as shown below: [23:16] Y [15:8] Cr (V) [7:0] Cb (U) The VOP takes this 24-bit 4:4:4 data bus and converts it to a 16-bit 4:2:2 data bus (the Y component on the high byte, the U/V components alternating on the low byte).
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6.7.6.5 33234H Video Processor Operating Modes Using the above formulas, the bit values are listed in Table 6-63. BT.656 Mode BT.656 is the basic standard that specifies the encoding of the control lines into the data bus. In this mode the separate control lines are encoded into the data bus as specified by Recommendation ITU-R BT.656. Each line begins with a Start of Active Video (SAV) header, and ends with an End of Active Video (EAV) header.
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33234H Video Processor VIP 2.0 Modes (8 or 16 bits) VIP 2.0 mode builds on VIP 1.1 with the following changes/ additions: — New Video Flags - The P Nibble is redefined as [NON_INT,REPEAT,Reserved,EXT_FLAG]. – NON_INT - 1 = non-interlaced source, 0 = interlaced source. – REPEAT - 1 = repeat field in 3:2 pull-down, 0 = not a repeat field (tied to 0). – EXT_FLAG - 1 = extra flag byte follows this EAV, 0 = no extra flag byte (this flag is always 0).
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33234H 6.7.6.6 New VIP 2.0 Video Flags Four bits are defined (shown in Table 6-64) by the VIP specification that allow the VIP slave to communicate field/ frame-specific information to the graphics chip during the video stream output. These flags are embedded in the lower nibble of the SAV or EAV header. These video flags allow the graphics chip to handle Bob and Weave, as well as 3:2 pull-down in hardware. Only bit 3 is implemented in the AMD Geode LX processor. Table 6-64.
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33234H Video Processor 6.7.7 Flat Panel Display Controller • 9+9 or 12+12-bit, and 24-bit 2 pixels per clock TFT panel support. 6.7.7.1 FP Functional Overview The flat panel (FP) display controller converts the digital RGB output of the Video Mixer block to digital output suitable for driving a TFT flat panel LCD. • Programmable dither, up to 64 levels. Features include: 6.7.7.
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33234H Video Processor 6.7.7.3 FP Functional Description The FP connects to the RGB port of the video mixer. Mode Selection The FP can be configured for operation with most standard TFT panels: LCD Interface The FP interfaces directly to industry standard 18-bit or 24bit active matrix thin-film-transistor (TFT). The digital RGB or video data that is supplied by the video logic is converted into a suitable format to drive a wide variety range of panels with variable bits.
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33234H Video Processor Table 6-66. Panel Output Signal Mapping (Continued) Pin Name TFT 9-Bit TFT 18-Bit TFT 24-Bit TFT 9+9-Bit TFT 12+12-Bit DOTCLK CLK CLK CLK CLK CLK HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC LDE LDE LDE LDE LDE ENLVDD ENLVDD ENLVDD ENLVDD ENLVDD LDEMOD VDDEN Maximum Frequency The FP will operate at a DOTCLK frequency of up to 170 MHz.
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33234H Video Processor X-Count[3:0] 000 001 010 011 100 101 110 111 000 10000000 01000000 01000000 10000000 01000000 01000000 10000000 01000000 001 01000000 10000000 01000000 01000000 01000000 10000000 01000000 01000000 010 01000000 01000000 10000000 01000000 01000000 01000000 10000000 01000000 011 01000000 01000000 01000000 10000000 01000000 01000000 01000000 10000000 100 10000000 01000000 01000000 01000000 10000000 01000000 01000000 01000000 101 01000000 10000000 01000000 01000000 010
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33234H Video Processor Y-Count [3:0] X-Count[3:0] X-Count[3:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 15 7 13 5 15 7 13 5 000 1 5 001 3 11 1 9 3 11 1 9 001 7 3 010 12 4 14 6 12 4 14 6 010 2 6 8 2 10 8 2 10 011 100 15 7 13 5 15 7 13 5 101 3 11 1 9 3 11 1 110 12 4 14 6 12 4 8 2 10 8 111 Y-Count [3:0] 011 6 1 5 4 7 3 1 5 2 6 1 5 4 7 3 4 7 3 2 6 1 5 2 6 4 7 3 2 6 1 5 4 7
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33234H Video Processor CRC Signature The FP contains hardware/logic that performs Cyclical Redundancy Checks (CRCs) on the panel data digital pipeline. This feature is used for error detection and makes it possible to capture a unique 24- or 32-bit signature for any given mode setup. An error in the dither pixel pipeline produces a different signature when compared to a known good signature value.
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33234H Video Processor 6.7.8 VP Resolution Table Supported CRT and flat panel resolutions of the VP are provided in Table 6-32 on page 281. All resolutions can be up to 8 bits per color, or 24 bits per pixel. In general, all display resolutions contained in VESA Monitor Timing Specifications Version 1.0 v0.8 are supported for CRT. Flat panels up to 1600x1200x60 are supported.
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33234H 6.8 Video Processor Register Descriptions Video Processor Register Descriptions This section provides information on the registers associated with the Video Processor: Standard GeodeLink Device (GLD) and Video Processor Specific MSRs (accessed via the RDMSR and WRMSR instructions), and two blocks of functional memory mapped registers (Video Processor and Flat Panel).
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33234H Video Processor Register Descriptions Table 6-71.
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33234H Video Processor Register Descriptions Table 6-71.
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33234H Video Processor Register Descriptions 6.8.1 Standard GeodeLink™ Device MSRs 6.8.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address 48002000h Type RO Reset Value 00000000_0013F0xxh GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 DEV_ID 4 3 2 1 0 REV_ID GLD_MSR_CAP Bit Descriptions Bit Name Description 63:24 RSVD Reserved.
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33234H Video Processor Register Descriptions GLD_MSR_CONFIG Bit Descriptions (Continued) Bit Name Description 15 FPC Simultaneous Flat Panel (or VOP) and CRT. Primary display is flat panel. Setting this bit activates the CRT DAC interface to allow simultaneous display of both panel and CRT. Leaving this bit reset forces the CRT DAC signals to zero. This bit is ignored if bits [5:3] of this register are set to 0 or 4. 14 IUV Interchange UV.
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33234H Video Processor Register Descriptions 6.8.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 48002002h Type R/W Reset Value 00000000_00000000h The Video Processor does not produce SMI interrupts, therefore this register is not used. Always write 0. 6.8.1.
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33234H Video Processor Register Descriptions 6.8.1.
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33234H Video Processor Register Descriptions 6.8.2 Video Processor Module Specific MSRs 6.8.2.
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33234H Video Processor Register Descriptions 6.8.2.
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33234H Video Processor Register Descriptions 6.8.3 Video Processor Module Control/Configuration Registers 6.8.3.
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33234H Video Processor Register Descriptions VCFG Bit Descriptions (Continued) Bit 5 Name Description SC_BYP Scaler Bypass. Bypass scaling math functions. Should only be used for non-scaled video outputs. Scale factors set to 10000h. 0: Scaler enabled. 1: Scaler disabled. 4 3:2 RSVD (RO) Reserved (Read Only). Reads back as 0. VID_FMT Video Format. Byte ordering of video data on the video input bus.
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33234H Video Processor Register Descriptions DCFG Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0. 31:28 SP Spares. Bits are read/write, but have no function. 27 RSVD (RO) Reserved (Read Only). Reads back as 0. 26 DAC_VREF Select CRT DAC VREF. Allows use of an external voltage reference for CRT DAC. 0: Disable external VREF. 1: Use external VREF. 25:22 21 RSVD (RO) Reserved (Read Only). Reads back as 0. GV_GAM Graphics/Video Gamma.
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33234H Video Processor Register Descriptions DCFG Bit Descriptions (Continued) Bit 2 Name Description VSYNC_EN CRT Vertical Sync Enable. Enables/disables CRT vertical sync (used for VESA DPMS support). 0: Disable. 1: Enable. 1 HSYNC_EN CRT Horizontal Sync Enable. Enables/disables CRT horizontal sync (used for VESA DPMS support). 0: Disable. 1: Enable. 0 CRT_EN CRT Enable. Enables the graphics display control logic. This bit is also used to reset the display logic. 0: Reset display control logic.
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33234H Video Processor Register Descriptions 6.8.3.4 Video Y Position (VY) VP Memory Offset 018h Type R/W Reset Value 00000000_00000000h VY Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD VID_Y_END 9 8 7 RSVD 6 5 4 3 2 1 0 VID_Y_START VY Bit Descriptions Bit Name Description 63:27 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions SCL Bit Descriptions Bit 30 Name GB (RO) Description GLIU Behind (Read Only). This bit set indicates the GLIU line buffer fill is falling behind the Dot display. This bit clears on read. This bit is typically set if during vertical downscale, the 2nd line buffer fill has not completed before the Dot display has started. This does not necessarily indicate an error, recovery is possible. 29:16 RSVD Reserved. 15 SP Spare. Bit is R/W but has no function.
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33234H Video Processor Register Descriptions VCK Bit Descriptions (Continued) Bit 23:0 Name Description VID_CLR_KEY Video Color Key. The video color key is a 24-bit RGB or YUV value. • If VG_CK (VP Memory Offset 008h[20]) is set to 0, the video pixel is selected within the target window if the corresponding graphics pixel matches the color key. The color key is an RGB value.
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33234H Video Processor Register Descriptions 6.8.3.8 Palette Address (PAR) VP Memory Offset 038h Type R/W Reset Value 00000000_000000xxh PAR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RSVD 5 4 3 2 1 0 PAL_ADDR PAR Bit Descriptions Bit Name Description 63:8 RSVD (RO) Reserved (Read Only). Reads back as 0. 7:0 PAL_ADDR Gamma Address.
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33234H Video Processor Register Descriptions 6.8.3.10 Saturation Scale (SLR) VP Memory Offset 048h Type R/W Reset Value 00000000_00000000h SLR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 9 8 SPARE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EN RSVD 7 6 5 4 3 2 1 0 SAT_SCALE SLR Bit Descriptions Bit 63:10 9 8 7:0 Name Description RSVD (RO) Reserved (Read Only). Reads back as 0. EN Enable.
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33234H Video Processor Register Descriptions 6.8.3.11 Miscellaneous (MISC) VP Memory Offset 050h Type R/W Reset Value 00000000_00000C00h MISC Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 8 7 6 5 4 3 2 1 RSVD 0 BYP_BOTH 9 DACPWRDN SP RSVD APWRDN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MISC Bit Descriptions Bit Name Description RSVD (RO) Reserved (Read Only). Reads back as 0. 12 SP Spare.
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33234H Video Processor Register Descriptions 6.8.3.12 CRT Clock Select (CCS) VP Memory Offset 058h Type R/W Reset Value 00000000_00000000h This register is made up of read only reserved bits and spare bits with no functions. 6.8.3.
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33234H Video Processor Register Descriptions VXS Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0. 31:20 X_ACC_INIT X Accumulator Initial Value. Load this value before each video line. Works with horizontal scaling, in case a sub-pixel offset is required prior to displaying video. Pad 4 LSBs with 0 when loading. 19:0 VID_X_SCL Video X Scale Factor.
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33234H Video Processor Register Descriptions 6.8.3.16 CRC Signature (CRC) VP Memory Offset 088h Type R/W Reset Value 00000000_00000000h CRC Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 8 7 6 5 4 3 2 1 SIGFR RSVD 9 0 SIGEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SIGVAL RSVD CRC Bit Descriptions Bit Name Description RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions 6.8.3.17 32-Bit CRC Signature (CRC32) VP Memory Offset 090h Type RO Reset Value 00000000_00000001h CRC32 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIG_VALUE CRC32 Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions VDE Bit Descriptions (Continued) Bit 17:16 Name Description A1P Alpha Window 1 Priority. Indicates the priority of alpha window 1. A higher number indicates a higher priority. Priority is used to determine display order for overlapping alpha windows. This field is reset by hardware to 00. 15 ALPHA_DRGB Enable Alpha on DRGB[31:24]. The source of the alpha value is the upper 8 bits [31:24] of the graphics input bus.
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33234H Video Processor Register Descriptions VDE Bit Descriptions (Continued) Bit 8 Name Description GFX_INS_ VIDEO Graphics Window inside Video Window. 0: Disable. The video window is assumed to be inside the graphics window. Outside the alpha window, graphics or video is displayed, depending on the result of color key comparison. 1: Enable. The graphics window is assumed to be inside the video window. Outside the alpha windows, video is displayed instead of graphics.
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33234H Video Processor Register Descriptions 6.8.3.20 Cursor Color Mask (CCM) VP Memory Offset 0A8h Type R/W Reset Value 00000000_00000000h CCM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 CUR_COLOR_MASK CCM Bit Descriptions Bit Name Description 63:24 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions 6.8.3.22 Cursor Color 2 (CC2) VP Memory Offset 0B8h Type R/W Reset Value 00000000_00000000h CC2 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 CUR_COLOR_REG2 CC2 Bit Descriptions Bit Name Description 63:24 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions 6.8.3.24 Alpha Window 1 Y Position (A1Y) VP Memory Offset 0C8h Type R/W Reset Value 00000000_00000000h A1Y Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD ALPHA1_Y_END 9 8 RSVD 7 6 5 4 3 2 1 0 ALPHA1_Y_START A1Y Bit Descriptions Bit Name Description 63:27 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions A1C Bit Descriptions Bit 63:25 24 Name Description RSVD (RO) Reserved (Read Only). Reads back as 0. ALPHA1_ COLOR_REG_ EN Alpha Window 1 Color Register Enable. Enable bit for the color key matching in alpha window 1. 0: Disable. If this bit is disabled, the alpha window is enabled, and VG_CK = 0 (VP Memory Offset 008h[20]); then where there is a color key match within the alpha window, video is displayed.
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33234H Video Processor Register Descriptions A1T Bit Descriptions Bit Name Description RSVD (RO) Reserved (Read Only). Reads back as 0. 18 PPA1_EN Per-Pixel Alpha Window 1 Enable. Enable per-pixel alpha functionality for alpha window 1. 0: Single alpha value for entire alpha window 1 (ALPHA1_MUL). 1: Each pixel has its own alpha value defined in the upper 8 bits of the graphics bus. 17 LOAD_ALPHA (WO) Load Alpha (Write Only).
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33234H Video Processor Register Descriptions 6.8.3.28 Alpha Window 2 Y Position (A2Y) VP Memory Offset 0E8h Type R/W Reset Value 00000000_00000000h A2Y Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD ALPHA2_Y_END 9 8 RSVD 7 6 5 4 3 2 1 0 ALPHA2_Y_START A2Y Bit Descriptions Bit Name Description 63:27 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions A2C Bit Descriptions Bit 63:25 24 Name Description RSVD (RO) Reserved (Read Only). Reads back as 0. ALPHA2_ COLOR_REG_ EN Alpha Window 2 Color Register Enable. Enable bit for the color key matching in alpha window 2. 0: Disable. If this bit is disabled, the alpha window is enabled, and VG_CK = 0 (VP Memory Offset 008h[20]); then where there is a color key match within the alpha window, video is displayed.
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33234H Video Processor Register Descriptions A2T Bit Descriptions (Continued) Bit Name Description 16 ALPHA2_WIN_ EN Alpha Window 2 Enable. Enable bit for alpha window 2. 15:8 ALPHA2_INC Alpha Window 2 Increment. Specifies the alpha value increment/decrement. This is a signed 8-bit value that is added to the alpha value for each frame. The MSB (bit 15) indicates the sign (i.e., increment or decrement).
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33234H Video Processor Register Descriptions 6.8.3.32 Alpha Window 3 Y Position (A3Y) VP Memory Offset 108h Type R/W Reset Value 00000000_00000000h A3Y Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD ALPHA3_Y_END 9 8 RSVD 7 6 5 4 3 2 1 0 ALPHA3_Y_START A3Y Bit Descriptions Bit Name Description 63:27 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions A3C Bit Descriptions Bit 63:25 24 Name Description RSVD (RO) Reserved (Read Only). Reads back as 0. ALPHA3_ COLOR_REG_ EN Alpha Window 3 Color Register Enable. Enable bit for the color key matching in alpha window 3. 0: Disable. If this bit is disabled, the alpha window is enabled, and VG_CK = 0 (VP Memory Offset 008h[20]); then where there is a color key match within the alpha window, video is displayed.
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33234H Video Processor Register Descriptions A3T Bit Descriptions (Continued) Bit Name Description 16 ALPHA3_WIN_ EN Alpha Window 3 Enable. Enable bit for alpha window 3. 15:8 ALPHA3_INC Alpha Window 3 Increment. Specifies the alpha value increment/decrement. This is a signed 8-bit value that is added to the alpha value for each frame. The MSB (bit 15) indicates the sign (i.e., increment or decrement).
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33234H Video Processor Register Descriptions 6.8.3.36 Alpha Watch (AWT) VP Memory Offset 128h Type RO Reset Value 00000000_00000000h Alpha values may be automatically incremented/decremented for successive frames. This register can be used to read alpha values that are being used in the current frame.
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33234H Video Processor Register Descriptions 6.8.3.38 Even Video Y Position (VYE) VP Memory Offset 138h Type R/W Reset Value 00000000_00000000h VYE Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD VID_Y_END 9 8 7 RSVD 6 5 4 3 2 1 0 VID_Y_START VYE Bit Descriptions Bit Name Description 63:27 RSVD (RO) Reserved (Read Only). Reads back as 0.
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33234H Video Processor Register Descriptions 6.8.3.40 Even Alpha Window 2 Y Position (A2YE) VP Memory Offset 148h Type R/W Reset Value 00000000_00000000h A2YE Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD ALPHA2_Y_END 9 8 RSVD 7 6 5 4 3 2 1 0 ALPHA2_Y_START A2YE Bit Descriptions Bit Name Description 63:27 RSVD (RO) Reserved (Read Only).
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33234H Video Processor Register Descriptions 6.8.3.42 Video Coefficient RAM (VCR) VP Memory Offset 1000h-1FFFh Type R/W Reset Value xxxxxxxx_xxxxxxxxh VCR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 VC3 VC2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 VC1 8 7 6 5 4 3 2 1 0 VC0 VCR Bit Descriptions Bit Name Description 63:48 VC3 Coefficient 3. Coefficient for tap 3 of filter.
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33234H Video Processor Register Descriptions PT1 Bit Descriptions (Continued) Bit Name Description 29 FP_HSYNC_ POL FP_HSYNC Input Polarity. Selects positive or negative polarity of the FP_HSYNC input. Program this bit to match the polarity of the incoming FP_HSYNC signal. Note that FP Memory Offset 408h[22] controls the polarity of the output HSYNC. 0: FP_HSYNC is normally low, transitioning high during sync interval.
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33234H Video Processor Register Descriptions 6.8.3.
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33234H Video Processor Register Descriptions PT2 Bit Descriptions (Continued) Bit Name Description 19 MCS Color/Mono Select. Selects color or monochrome LCD panel. 0: Color. 1: Monochrome. 18:16 PIXF Pixel Output Format. These bits define the pixel output format. The selection of the pixel output format determines how the pixel data is formatted before being sent on to the DRGB pins. These settings also determine the SHFCLK frequency for the specific panel.
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33234H Video Processor Register Descriptions PM Bit Descriptions (Continued) Bit Name Description 25 D Display Off Control Source. Selects how DISPEN is controlled. Independent control may be used to disable the backlight to save power even if the panel is otherwise ON. 0: DISPEN is controlled by with the power up/down sequence. 1: DISPEN is controlled independently of the power sequence. 24 P Panel Power On. Selects whether the panel is powered down or up following the power sequence mechanism.
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33234H Video Processor Register Descriptions 6.8.3.46 Dither and Frame Rate Control (DFC) VP Memory Offset 418h Type R/W Reset Value 00000000_00000000h DFC Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 9 8 RSVD 7 6 5 BC 4 3 2 1 DBS 0 DENB RVRS RRS RSVD RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DFC Bit Descriptions Bit 63:13 12 Name Description RSVD (RO) Reserved (Read Only).
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33234H Video Processor Register Descriptions DFC Bit Descriptions (Continued) Bit Name Description 0 DENB Dithering Enable. Enable/disable dithering. The dither bit must be enabled in order for dither RAM reads or writes to occur. When this bit is cleared, the internal dither RAM is powered down, which saves power. 0: Dither disable. The dithering function is turned off. When the dither is disabled the Dithering Bits Select (bits [3:1]) do not have any effect and the dither RAM is not accessible.
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33234H Video Processor Register Descriptions 6.8.3.48 Dither Memory Data (DMD) VP Memory Offset 450h Type R/W Reset Value 00000000_00000000h DMD Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDAT DMD Bit Descriptions Bit Name Description 63:32 RSVD (RO) Reserved (Read Only). Reads back as 0. 31:0 RDAT RAM Data.
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33234H Video Processor Register Descriptions 6.8.3.50 32-Bit Panel CRC (CRC32) VP Memory Offset 468h Type RO Reset Value 00000000_00000001h CRC32 Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRC CRC32 Bit Descriptions Bit Name Description 63:32 RSVD Reserved. Reads back as 0. 31:0 CRC 32-Bit CRC.
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33234H Video Processor Register Descriptions VOP_CONFIG Bit Descriptions (Continued) Bit Name Description 18 INV VS POL Invert VSYNC Polarity. Set to 1 to invert polarity of VSYNC (for 601 mode only). 17 INV HS POL Invert HSYNC Polarity. Set to 1 to invert polarity of HSYNC (for 601 mode only). 16 UV SWAP UV Swap. 0: No swap. 1: Swap lowest byte with next lowest byte in [23:0] input data stream. This is essentially swapping the U and V, and if in RGB, swapping G and B.
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33234H Video Processor Register Descriptions VOP_CONFIG Bit Descriptions (Continued) Bit Name 6 SC120X_MODE Description SC120X Compatible Mode. Creates EAV/SAV codes consistent with the AMD Geode™ SC1200 and SC1201 processor’s VOP. 0: Normal mode. 1: SC1200/SC1201 compatible mode. Set to 1 for BT.601 mode. 5:4 422_MODE 4:4:4 to 4:2:2 Conversion Algorithm. Selects which method is used to convert 4:4:4 data to 4:2:2. 00: 4:2:2 Co-sited. 01: 4:2:2 Interspersed (U,V samples from respective co-samples).
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33234H 6.9 Video Input Port 6.9.1 Features Video Input Port • VESA 1.1, 2.0 and BT.601, BT.656 compliant, 150 MHz (excludes host interface). — Standard 9 or 17 pin interface (8/16 data + clock) — 8/16-bit BT.656 video — TASK A/B video and VBI (two video streams) — 8/16-bit ancillary data — HD capable (up to 1280x720 progressive scan, 1920x1080 interlaced) — VIP 1.
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33234H Video Input Port 6.9.
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33234H 6.9.2.1 Input Formatter The Input Formatter receives 8- or 16-bit VIP input data, It does a 4:2:2 to 4:2:0 translation (if enabled) and formats it into either linear data or planar data for storage in the Capture RAM. 6.9.2.2 Input Control The Input Control block operates in either VIP 2.0 16-bit mode, VIP 2.0 8-bit mode, VIP 1.1 compatible mode, Message Passing mode, Data Streaming mode, or BT.601 Input mode.
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Video Input Port 6.9.3 Functional Description The Video Input Port (VIP) receives 8- or 16-bit video or ancillary data, 8-bit message data, or 8-bit raw video, and passes it to data buffers located in system memory. The primary operational mode is as a compliant VIP 2.0 slave. The VIP 2.0 specification defines the protocol for receiving video, VBI, and ancillary data. The addition of the Message Passing and Data Streaming modes provide flexibility in receiving non-VIP 2.0 compliant data streams.
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33234H 6.9.5 Video Input Port Mode 1a,b,c - VIP Input Data (simplified BT.656) The VIP 2.0 specification describes an 8- or 16-bit data stream incorporating both control and data. The data/control is delivered in packets. There are two different packet types, SAV/EAV and ancillary packets. The specification also requires backwards compatibility to VIP 1.1 data formats. Three different VIP data modes are supported: VIP 1.1 compatible mode, VIP 2.0 8-bit mode, and VIP 2.0 16bit mode.
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33234H Video Input Port VIP 2.0 Video Flags Two new video flags are defined in the VIP 2.0 specification to decode whether the input video is interlaced or noninterlaced and whether the data is merely a repeated field. These flags are meant to enable VIP to handle Bob and Weave, as well as 3:2 pull down in hardware. The new flags are embedded in the lower nibble of the SAV and EAV header. The non-interlace flag NON_INT (bit 3 of the status WORD) is ignored by the VIP.
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33234H Line 4 Video Input Port Blanking (VBI Data) Line 20(V = 0) Field 1 (F = 0) Odd Field 1 Active Video Line 264 (V = 1) Line 266 Line Number F V H H (EAV) (SAV) 1-3 1 1 1 0 4-19 0 1 1 0 20-263 0 0 1 0 264-265 0 1 1 0 266-282 1 1 1 0 283-525 1 0 1 0 Blanking (VBI Data) Line 283 (V = 0) Field 2 (F = 1) Even Field 2 Active Video Line 525 (V = 0) Line 1 (V = 1) Line 3 H=1 EAV H=0 SAV In VIP 1.1 mode, the T,F,V video flags are only captured from the EAV code.
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33234H Video Input Port 6.9.5.2 Ancillary Packets Ancillary packets are received during vertical and/or horizontal blanking. The ancillary packet has a 6-byte header of 00-FF-FF-DID-SDID-NN. The first three bytes are the pre-amble. The DID and SDID bytes are the data identifier and the secondary data identifier bytes. The NN byte is the data count and specifies the length of the ancillary data block in DWORDs (4-byte blocks).
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33234H 6.9.6 Video Input Port Message Passing Mode The Message Passing mode (MSG) allows an external device to pass raw data packets to the AMD Geode LX processor system memory (see Figure 6-43). In Message Passing mode, VID8 is redefined as a start message indication and VID9 is redefined as an end message indication. Video data reception (SAV/EAV packets and ancillary packets) is disabled while in Message Passing mode. 6.9.
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33234H Video Input Port 6.9.8 BT.601 Mode BT.601 mode allows reception of 8- or 16-bit video input which consists of HSYNC, VSYNC, and 8/16 bit data. Vertical and horizontal start/stop registers provide the information for data capture in each field/frame. The BT.656 SAV/ EAV codes (if present) are ignored. Frame/line timing is derived from the HSYNC and VSYNC inputs only. Odd/ even field is determined by the leading edges of VSYNC and HSYNC. Default field detection is shown in Figure 645.
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33234H Video Input Port . ACTIVE LOW HSYNC/VSYNC (HSYNC Polarity = 0 / VSYNC Polarity = 0) HSYNC odd_field_detect_start line #1 field_detect_duration VSYNC (for odd field) odd field VSYNC (for even field) even field ACTIVE HIGH HSYNC/VSYNC (HSYNC Polarity = 1 / VSYNC Polarity = 1) HSYNC odd_field_detect_start line #1 field_detect_duration VSYNC (for odd field) odd field VSYNC (for even field) even field Figure 6-46. BT.
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33234H Video Input Port VBI Data 2 3 1 HSYNC VSYNC (even field) C=4 VSYNC (odd field) E=4 4 Video Data 5 6 7 8 D=7 F=7 VSYNC G=2 H=3 C - vertical_start for 601 odd field (VIP Memory Offset 6Ch[11:0]) D - vertical_end for 601 odd field (VIP Memory Offset 6Ch[27:16]) E - vertical_start for 601 even field (VIP Memory Offset 48h[11:0]) F - vertical_end for 601 even field (VIP Memory Offset 48h[27:16]) G - vbi_start for 601 (VIP Memory Offset 44h[11:0]) H - vbi_end for 601 (VIP Memory Offset 40h[11:
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33234H Video Input Port YUV 4:2:2 1 2 3 YUV 4:2:0 4 5 6 1 1 1 2 2 3 3 4 4 5 5 6 6 7 7 2 3 4 5 6 Progressive scan - Discard even line UV values (single frame buffer in system memory) YUV 4:2:2 1 2 3 YUV 4:2:0 4 5 6 1 1 [1] 2 2 3 [2] 4 1 2 3 4 5 6 1 2 3 4 5 6 3 [3] [1] 4 [2] [3] Interlaced (Bob) - Discard even line UV values in both input fields (odd and even field buffers in system memory) YUV 4:2:2 1 2 3 4 YUV 4:2:0 5 6 1 1 1 [1] 2 2 3
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33234H Video Input Port 6.9.10 Software Model The VIP receives data and stores it into system memory. The VIP input modes with associated data types are shown in Table 6-74. VIP 2.0 is the VESA VIP 2.0 Level I (8-bit) standard or the VESA VIP 2.0 Level II (16-bit) standard. VIP 1.1 is the VESA (8-bit) standard in which only a single video stream is supported and the TASK bit is used to distinguish between video and VBI data.
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33234H 6.9.10.1 Video Data Buffers Video data buffers can be organized in linear or planar formats. Linear buffers pack YUV values contiguous in memory. Planar buffers have separate subbuffers for each set of YUV values in a field or frame. The VIP Control 1 register (VIP Memory Offset 00h[4]) determines if the video storage format is linear or planar.
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33234H Video Input Port vid_base vid_base + vid_pitch vid_base + 2 X vid_pitch 3 2 1 0 Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb 00* 00* 00* 00* * line is 00 filled if not QWORD aligned Y Cr Y Cb line 2 start Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb 00* 00* 00* 00* Y Cr Y Cb line 1 start (buffer start) line 3 start * Similar buffer can exist for Task A odd video, Task A even video, Task B odd video, Task B even video, Task A odd VBI dat
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33234H Video Input Port Y pitch = task_A_vid_pitch vid_base line #1 Y values Y Buffer vid_base + U_buffer_even_offset line #1 U values U pitch = task_A_U_pitch U Buffer vid_base +V_buffer_even_offset line #1 V values (all base registers are 8-byte aligned) V pitch = task_A_V_pitch V Buffer task_A_UV_pitch ** Similar buffers can exist for Task A even video ** Odd/even de-interlacing is not supported for Task B (Task B shares pointers between odd/even fields) Note: Line lengths, which are not divis
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33234H Video Input Port anc_message_base (8-byte aligned) 8/16-BIT ANCILLARY DATA 3 2 1 0 DID FF FF 00 data data data data data data data data data data data data data data 00* CS data data DID FF FF 00 data data data data data data data data data data data data data data data data data data data data data data 00* CS data data * packet is 00 filled if not QWORD aligned data data NN=7 SID packet 3 start 3 10-BIT ANCILLARY DATA 2 packet 1 s
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33234H 6.9.11 Bob and Weave Bob and Weave are two methods of outputting interlaced video, captured by the VIP, in a progressive scan format. An example of this is when VIP receives 30 Hz interlaced (NTSC format) and the data is to be displayed on a TFT panel that requires progressive scan with a 60-85 Hz refresh rate. In the Bob method, VIP stores the odd and even fields in separate buffers.
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33234H Video Input Port Vertical Timing Error (Frame or Address Error) /Message Missed Error - This error indicates a frame error or an address error. A frame error occurs when the time between VSYNCs exceeds the window defined by the VIP_SYNC_ERR_COUNT register (VIP Memory Offset 78h). The VIP_SYNC_ERR_COUNT register must be programmed. An address error occurs when the GLIU address equals or exceeds the address programmed in the VIP_MAX_ADDR register (VIP Memory Offset 14h).
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33234H 6.10 Video Input Port Register Descriptions Video Input Port Register Descriptions The registers associated with the VIP are the Standard GeodeLink Device (GLD) MSRs (accessed via the RDMSR and WRMSR instructions) and VIP Configuration/Control Registers. Table 6-75 and Table 6-76 are register summary tables that include reset values and page references where the bit descriptions are provided. Note: The MSR address is derived from the perspective of the CPU Core. See Section 4.
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Video Input Port Register Descriptions 33234H Table 6-76.
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33234H 6.10.1 Video Input Port Register Descriptions Standard GeodeLink™ Device (GLD) MSRs 6.10.1.
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33234H Video Input Port Register Descriptions 6.10.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 54002002h Type R/W Reset Value 000000000_ xxxx7FFFh GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD RSVD RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SMI_STATUS 9 8 7 6 5 4 3 2 1 0 SMI_MASK GLD_MSR_SMI Bit Descriptions Bit Name Description 63:31 RSVD Reserved.
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33234H Video Input Port Register Descriptions 6.10.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 54002003h Type R/W Reset Value 000000000_ 00000000h GLD_MSR_ERROR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD E1 E0 9 8 RSVD 7 6 5 4 3 2 1 0 EM0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EM1 RSVD GLD_MSR_ERROR Bit Descriptions Bit Name Description 63:18 RSVD Reserved. E1 Error Status 1.
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33234H Video Input Port Register Descriptions 6.10.1.5 GLD Power Management Register (GLD_MSR_PM) MSR Address 54002004h Type R/W Reset Value 000000000_ 00000005h GLD_MSR_PM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 4 3 2 1 0 0 P1 0 P0 GLD_MSR_PM Bit Descriptions Bit Name Description 63:4 RSVD Reserved. 3 RSVD Reserved.
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33234H 6.10.2 Video Input Port Register Descriptions VIP Control/Configuration Registers 6.10.2.1 VIP Control Register 1 (VIP_CTL_REG1) VIP Memory Offset 00h Type R/W Reset Value 42000001h VIP_CTL_REG1 Register Map ANC_FF VID_FF ERR_DETECT NI MB DZ DD 9 DT_EN 8 7 6 5 4 3 2 1 RUN_MODE P VIP_MODE 0 VRST 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VIP_CTL_REG1 Bit Descriptions Bit 31:29 Name Description ANC_FF Ancillary FIFO Flush.
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Video Input Port Register Descriptions 33234H VIP_CTL_REG1 Bit Descriptions (Continued) Bit Name Description 19 NI Non-Interlaced Video Input. This bit determines if the start/end-of-frame event occurs each field (for non-interlaced video) or at the end of the odd field (for interlaced video). The start/end-of-frame indication is used as the start/end-of-frame indication for the Run Mode Capture. When in 601 input modes, the NI bit determines if separate vertical backporch values are used.
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33234H Video Input Port Register Descriptions VIP_CTL_REG1 Bit Descriptions (Continued) Bit Name Description 3:1 VIP_MODE VIP Operating Mode. 000: IDLE. This mode forces VID[15:0] to 0 from pads to VIP. 001: VIP 2.0 8-bit mode. 010: VIP 2.0 16-bit. 011: VIP 1.1 8-bit. 100: Message Passing. 101: Data Streaming. 110: 601 type 8-bit mode. 111: 601 type 16-bit mode. 0 VRST VIP Reset. When set to 1, this bit causes the VIP input logic to be reset. The control registers and base registers are not reset.
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Video Input Port Register Descriptions 33234H VIP_CTL_REG2 Bit Descriptions (Continued) Bit Name Description 26 ANCPEN Ancillary Parity Check Enable. When set to 1, ancillary DID, SDID, NN, and check sum bytes are checked for even parity. The error is reported on MSR 4002002h[23]. When this bit is 0, the Ancillary Checksum or Parity Error bit only indicates ancillary checksum errors. 25 LPB VOP to VIP Loopback. When set to 1, the VOP clock and data are used as the clock and data inputs to the VIP.
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33234H Video Input Port Register Descriptions 6.10.2.3 VIP Status (VIP_STATUS) VIP Memory Offset 08h Type R/W Reset Value xxxxxxxxh VIP_STATUS Register Map 8 6 5 4 3 F V FE RSVD GLWC B1_FULL 7 2 1 0 RUN_STATUS 9 RSVD B2_FULL RSVD BRNU SO DPC RSVD RSVD FPE APC MSG_BERR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VIP_STATUS Bit Descriptions Bit 31:24 23 22:20 Name Description APC (RO) Ancillary Packet Count (Read Only).
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Video Input Port Register Descriptions 33234H VIP_STATUS Bit Descriptions (Continued) Bit Name Description 14 MSG_BERR Message Buffer Error. 0: No error. 1: Message buffer was overwritten. This occurs when both msg buffers are full and a msg/dstrm packet is received. Writing a 1 to the bit resets it to 0. 13 B2_FULL MSG Buffer 2 Full. 0: Buffer 2 empty. 1: Buffer 2 full. Writing a 1 to the bit resets it to 0. 12 B1_FULL MSG Buffer 1 Full. 0: Buffer 1 empty. 1: Buffer 1 full.
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33234H Video Input Port Register Descriptions 6.10.2.4 VIP Interrupt (VIP_INT) VIP Memory Offset 0Ch Type R/W Reset Value xxxxFFFEh VIP_INT Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INT_STATUS 9 8 7 6 5 4 3 2 1 0 INT_MASK VIP_INT Bit Descriptions Bit 31:16 Name Description INT_STATUS VIP Interrupt Status. 0: INT not pending. 1: INT pending. Writing a 1 to this bit clears the status. Bit 30: FIFO line wrap error. Bit 29: FIFO overflow error.
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33234H Video Input Port Register Descriptions 6.10.2.5 VIP Current/Target (VIP_CUR_TAR) VIP Memory Offset 10h Type R/W Reset Value 00000000h VIP_CUR_TAR Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LINE_TARGET 9 8 7 6 5 4 3 2 1 0 CURRENT_LINE VIP_CUR_TAR Register Bit Descriptions Bit Name Description 31:16 LINE_TARGET Line Target. Indicates the video line to generate an interrupt on. 15:0 CURRENT_ LINE (RO) Current Line (Read Only).
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33234H Video Input Port Register Descriptions 6.10.2.7 VIP Task A Video Even Base Address (VIP_TASK_A_VID_EVEN_BASE) VIP Memory Offset 18h Type R/W Reset Value 00000000h VIP_TASK_A_VID_EVEN_BASE Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 TASK_A_VIDEO_EVEN_BASE_ADDRESS 3 2 1 0 Program to 00000 VIP_TASK_A_VID_EVEN_BASE Bit Descriptions Bit 31:0 Name Description TASK_A VIDEO_EVEN BASE Task A Video Even Base Address.
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33234H Video Input Port Register Descriptions 6.10.2.9 VIP Task A VBI Even Base Address (VIP_TASK_A_VBI_EVEN_BASE) VIP Memory Offset 20h Type R/W Reset Value 00000000h VIP_TASK_A_VBI_EVEN_BASE Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TASK_A_VBI_DATA_EVEN_BASE 4 3 2 1 0 Program to 00000 VIP_TASK_A_VBI_EVEN_BASE Bit Descriptions Bit 31:0 Name Description TASK_A_VBI_E VEN_BASE Task AVBI Even Base Address.
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33234H Video Input Port Register Descriptions 6.10.2.11 VIP Task A Video Pitch (VIP_TASK_A_VID_PITCH) VIP Memory Offset 28h Type R/W Reset Value 00000000h VIP_TASK_A_VID_PITCH Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TASK_A_UV_PITCH Program to 00000 9 8 7 6 5 TASK_A_VIDEO_PITCH 4 3 2 1 0 Program to 00000 VIP_TASK_A_VID_PITCH Bit Descriptions Bit Name Description 31:16 TASK_A_UV_ PITCH Task A UV Pitch.
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33234H Video Input Port Register Descriptions VIP_CONTRL_REG3 Bit Descriptions (Continued) Bit 7 Name Description EFD Even Field UV Decimation. When set to 1, the U and V values of the even frame will be discarded. Note: The DD bit (VIP Memory Offset 00h[16]) should be set to 1 or even lines will also be decimated. 6 TP Task Polarity. When set to 1, the input TASK bit is inverted. 5 VP VSYNC Polarity.
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33234H Video Input Port Register Descriptions 6.10.2.14 VIP Task A U Offset (VIP_TASK_A_U_OFFSET) VIP Memory Offset 34h Type R/W Reset Value 00000000h VIP_TASK_A_U_OFFSET Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Task A U Odd Offset 4 3 2 1 0 Program to 00000 VIP_TASK_A_U_OFFSET Bit Descriptions Bit 31:0 Name Description Task A U Odd Offset Task A U Odd Offset.
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33234H Video Input Port Register Descriptions 6.10.2.
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33234H Video Input Port Register Descriptions VIP_TASK_B_VBI_EVEN_BASE_VBI_END Bit Descriptions (Continued) Bit 11:0 Name Description VBI_END VBI End. This register is redefined in BT.601 mode. In BT.601 type input modes, timing is derived from the external HSYNC and VSYNC inputs. This value specifies what line the VBI data ends in each field/frame. The end of VBI data is reached when the number of lines from the falling edge of VSYNC equals this value. See Figure 6-48 "BT.
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33234H Video Input Port Register Descriptions VIP_TASK_B_DATA_PITCH_VERT_START_EVEN BIT Descriptions (Continued) Bit 27:16 Name Description VERTICAL_ END_EVEN Vertical End Even. This register is redefined in BT.601 mode. In BT.601 type input modes timing is derived from the external HSYNC and VSYNC inputs. This value specifies the last line of the even field captured in interlaced modes. This value is ignored when the NI bit (VIP Memory Offset 00h[19]) is set (indicating non-interlaced input).
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33234H Video Input Port Register Descriptions 6.10.2.21 VIP Task B U Offset (VIP_TASK_B_U_OFFSET) VIP Memory Offset 54h Type R/W Reset Value 00000000h VIP_TASK_B_U_OFFSET Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TASK_B_U_OFFSET 4 3 2 1 0 Program to 00000 VIP_TASK_B_U_OFFSET Bit Descriptions Bit 31:0 Name Description TASK_B_U_ OFFSET Task B U Offset.
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33234H Video Input Port Register Descriptions 6.10.2.23 VIP Ancillary Data/Message Passing/Data Streaming Buffer 2 Base Address (VIP_ANC_MSG_2_BASE) VIP Memory Offset 5Ch Type R/W Reset Value 00000000h VIP_ANC_MSG_2_BASE Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 ANC_MSG_2_BASE 4 3 2 1 0 Program to 00000 VIP_ANC_MSG_2_BASE Bit Descriptions Bit 31:0 Name Description ANC_MSG_2_ BASE Message Passing Data/Data Streaming Base Address.
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33234H Video Input Port Register Descriptions 6.10.2.25 VIP Page Offset/ Page Count (VIP_PAGE_OFFSET) VIP Memory Offset 68h Type R/W Reset Value 00000000h VIP_PAGE_OFFSET Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 PAGE_OFFSET 3 2 1 0 Program to 00000 VIP_PAGE_OFFSET Bit Descriptions Bit 31:0 Name Description PAGE_OFFSET Page Offset. This register specifies the offset to the next page of buffer data.
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33234H Video Input Port Register Descriptions 6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR) VIP Memory Offset 70h Type R/W Reset Value 00000000h VIP_FIFO_R_W_ADDR Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSVD 6 5 4 3 2 1 0 FIFO_ADDRESS VIP_FIFO_R_W_ADDR Bit Descriptions Bit Name Description 31:9 RSVD Reserved. Set to 0. 8:0 FIFO_ADDRESS FIFO ADDRESS. FIFO address for which a FIFO read or write occurs.
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33234H Video Input Port Register Descriptions 6.10.2.29 VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT) VIP Memory Offset 78h Type R/W Reset Value 00000000h VIP_SYNC_ERR_COUNT Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VERTICAL_WINDOW 9 8 7 6 5 4 3 2 1 0 VERTICAL_COUNT VIP_SYNC_ERR_COUNT Bit Descriptions Bit Name Description 31:24 VERTICAL_ WINDOW Vertical Window.
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33234H Video Input Port Register Descriptions 6.10.2.31 VIP Task A V Even Offset (VIP_TASK_A_V_EVEN_OFFSET) VIP Memory Offset 80h Type R/W Reset Value 00000000h VIP_TASK_A_V_EVEN_OFFSET Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TASK_A_V_EVEN_OFFSET 7 6 5 4 3 2 1 0 Program to 00000 VIP_TASK_A_V_EVEN_OFFSET Bit Descriptions Bit 31:0 Name Description TASK_A_V_ EVEN_OFFSET Task A V Even Offset.
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33234H 6.11 Security Block Security Block — Programmable “Hidden” AES key — Can use interrupts, SMIs, or be polled for completion status — Memory mapped register interface The Security Block provides a hardware Advanced Encryption Standard (AES) encryption/decryption engine and interface for accessing EEPROM memory for storing unique IDs and/or security keys. The AES and EEPROM sections have separate control registers but share a single set of interrupt registers. 6.11.
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Security Block 6.11.2 Functional Description The AES engine provides ECB and CBC 128-bit hardware encryption and decryption for the AMD Geode LX processor using the Advanced Encryption Standard algorithm. The Security Block has two key sources. One is a hidden 128-bit key stored in non-volatile memory. It is expected that this key is loaded into the non-volatile memory once at the factory and the memory is locked to prevent future writes.
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33234H Security Block 6.11.2.1 EEPROM ID Interface The EEPROM ID interface provides an interface to an EEPROM non-volatile memory available for storing ID numbers, keys, or other security related information. The EEPROM ID interface consists of a 2K (256-byte) array with 2 bytes reserved for EEPROM control state, 238 bytes are available as general purpose non-volatile storage, and 16 bytes reserved for use as a hidden key for the AES engine.
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33234H Security Block Register Descriptions 6.12 Security Block Register Descriptions This section provides information on the registers associated with the Security Block (SB), including the Standard GeodeLink Device (GLD) MSRs, the Security Block Specific MSRs (accessed via the RDMSR and WRMSR instructions), and the Security Block Configuration/Control registers.
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33234H Security Block Register Descriptions Table 6-80.
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33234H Security Block Register Descriptions 6.12.1 Standard GeodeLink™ (GLD) Device MSRs 6.12.1.
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33234H Security Block Register Descriptions 6.12.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 58002002h Type R/W Reset Value 00000000_00000007h GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SMI_STAT US 9 8 7 6 RSVD 5 4 3 2 1 0 SMI_MASK GLD_MSR_SMI Bit Descriptions Bit Name Description 63:35 RSVD Reserved. 34:32 SMI_STATUS SMI Status.
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33234H Security Block Register Descriptions GLD_MSR_ERROR Register Map 6 5 4 3 2 RSVD AES_ERR_STATUS 7 0 1 AES_ERR_MASK 8 RA_ERR_STATUS RSVD 9 RSVD RA_ERR_MASK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RB_ERR_STATUS RSVD RB_ERR_MASK 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 GLD_MSR_Error Bit Descriptions Bit Name Description 63:37 RSVD Reserved. 36 RB_ERR_ STATUS Response B Error Status.
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33234H Security Block Register Descriptions 6.12.1.5 GLD Power Management MSR (GLD_MSR_PM) MSR Address 58002004h Type R/W Reset Value 00000000_00000015h GLD_MSR_PM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 6 5 4 3 2 1 0 PMD0 7 RSVD 8 PMD1 RSVD 9 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PMD2 RSVD GLD_MSR_PM Bit Descriptions Bit Name Description 63:5 RSVD Reserved.
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33234H Security Block Register Descriptions 6.12.2 Security Block Specific MSRs 6.12.2.
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33234H Security Block Register Descriptions GLD_MSR_CTRL Bit Descriptions (Continued) Bit Name Description 2 SBI Swap Bits. This bit controls a bit-swapping feature within the AES module. When set, the bits within each byte are swapped on both AES DMA reads and writes. Bit 7 is swapped with bit 0, bit 6 is swapped with 1, etc. Asserting this bit does not affect the slave operations to AES registers, (including the writable key), nor does it affect EEPROM operations.
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33234H Security Block Register Descriptions SB_CTL_A Register Bit Descriptions (Continued) Bit 0 Name Description STA Start for A Pointer. When set, this bit commands the AES to start a new operation based on the current control register setting and the settings in SB Memory Offset 010h and 014h. This bit is reset automatically when the operation completes.
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33234H Security Block Register Descriptions 6.12.3.3 SB AES Interrupt (SB_AES_INT) SB Memory Offset 008h Type R/W Reset Value 00000007h SB_AES_INT Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RSVD 17 16 15 14 13 12 11 10 INT_STATUS 9 8 7 6 5 4 3 RSVD 2 1 0 INT_MASK SB_AES_INT Register Bit Descriptions Bit Name Description 31:19 RSVD Reserved. 18:16 INT_STATUS AES Interrupt Status. 0: INT not pending. 1: INT pending. Writing a 1 to this bit clears the status.
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33234H Security Block Register Descriptions 6.12.3.5 SB Destination A (SB_DEST_A) SB Memory Offset 014h Type R/W Reset Value 00000000h SB_DEST_A Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Destination A 2 1 0 RSVD SB_DEST_A Register Bit Descriptions Bit Name Description 31:4 DEST_A Destination A. The Destination field is a 32-bit pointer to system memory.
PAGE 524
33234H Security Block Register Descriptions 6.12.3.7 SB Source B (SB_SOURCE_B) SB Memory Offset 020h Type R/W Reset Value 00000000h SB_SOURCE_B Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 SOURCE_B 2 1 0 RSVD SB_SOURCE_B Register Bit Descriptions Bit Name Description 31:4 SOURCE_B Source B. The Source field is a 32-bit pointer to system memory. It points to the start of data to be encrypted or decrypted.
PAGE 525
33234H Security Block Register Descriptions 6.12.3.9 SB Length B (SB_LENGTH_B) SB Memory Offset 028h Type R/W Reset Value 00000000h SB_LENGTH_B Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 LENGTH_B 2 1 0 RSVD SB_LENGTH_B Register Bit Descriptions Bit Name Description 31:4 LENGTH_B Length B. The Length field is a 32-bit value that describes the number of bytes to be encrypted or decrypted in the next operation using pointer set B.
PAGE 526
33234H Security Block Register Descriptions 6.12.3.11 SB Writable Key 1 (SB_WKEY_1) SB Memory Offset 034h Type WO Reset Value 00000000h SB_WKEY_1 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY_1[63:32] SB_WKEY_1 Bit Descriptions Bit 31:0 Name Description WKEY_1 Writable Key 1. Bits [63:32] of the Writable Key for the Security Block. This register should not be changed during an AES encryption or decryption operation.
PAGE 527
33234H Security Block Register Descriptions 6.12.3.13 SB Writable Key 3 (SB_WKEY_3) SB Memory Offset 03Ch Type WO Reset Value 00000000h SB_WKEY_3 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKEY_3[127:96] SB_WKEY_3 Bit Descriptions Bit 31:0 Name Description Writable Key 3 Writable Key 3. Bits [127:96] of the Writable Key for the Security Block. This register should not be changed during an AES encryption or decryption operation.
PAGE 528
33234H Security Block Register Descriptions 6.12.3.15 SB CBC Initialization Vector 1 (SB_CBC_IV_1) SB Memory Offset 044h Type R/W Reset Value 00000000h SB_CBC_IV_1 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBC_IV_1[63:32] SB_CBC_IV_1 Bit Descriptions Bit 31:0 Name Description IV[63:32] CBC Initialization Vector 1 [63:32]. Bits [63:32] of the IV for the CBC AES mode. Change this register only when both A and B channels are IDLE.
PAGE 529
33234H Security Block Register Descriptions 6.12.3.18 SB Random Number (SB_RANDOM_NUM) SB Memory Offset 050h Type RO Reset Value 00000000h SB_RANDOM_NUM Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RANDOM_NUM SB Random Number Bit Descriptions Bit 31:0 Name Description RANDOM_ NUM Random Number. Returns a 32-bit random number. Check the TRNG_VALID bit (SB Memory Offset 054h[0]) before reading this register.
PAGE 530
33234H Security Block Register Descriptions 6.12.3.20 SB EEPROM Command (SB_EEPROM_COMM) SB Memory Offset 800h Type R/W Reset Value 00000000h 6 5 4 3 2 1 0 RSVD WR ST 8 EX 9 KV RSVD SL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 HKD SB_EEPROM_COMM Register Map 7 SB_EEPROM_COMM Bit Descriptions 530 Bit Name Description 31:8 RSVD Reserved. 7:6 RSVD Reserved. These bits are implemented but reserved for future use.
PAGE 531
33234H Security Block Register Descriptions 6.12.3.21 SB EEPROM Address (SB_EEPROM_ADDR) SB Memory Offset 804h Type R/W Reset Value 000000FFh SB_EEPROM_ADDR Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD 9 8 7 6 5 RSVD 4 3 2 1 0 EE_ADDR SB_EEPROM_ADDR Bit Descriptions Bit Name Description 31:11 RSVD Reserved. 10:8 RSVD Reserved. These bits are reserved for future expansion of the EEPROM size and must be written to 0. 7:0 EE_ADDR EEPROM Address.
PAGE 532
33234H Security Block Register Descriptions 6.12.3.23 SB EEPROM Security State (SB_EEPROM_SEC_STATE) SB Memory Offset 80Ch Type RO Reset Value 00000000h This read only register contains the current state of the access control bits for controlling reads and writes from/to the EEPROM. It is reloaded from the EEPROM array after every reset. The initial state of the EEPROM is all ones. Therefore the unlocked state of the control bits must be one.
PAGE 533
33234H GeodeLink™ Control Processor 6.13 GeodeLink™ Control Processor The GeodeLink Control Processor (GLCP) functionality covers these areas (see Figure 6-55): • Scan chain control • JTAG interface to boundary scan, BIST, GLIU1, and debug logic • Power (clock) control • Reset logic • PLL control • Internal logic analyzer/debugger • 1KB FIFO/SRAM • Compliant with GLIU System Architecture Specification v1.
PAGE 534
33234H GeodeLink™ Control Processor Table 6-81. TAP Control Instructions (25-Bit IR) Instruction DR Length 123FFFAh IR Name Description 8 BYPASS_MODES This register is read/write.
PAGE 535
33234H GeodeLink™ Control Processor EXTEST JTAG Instruction The EXTEST instruction accesses the boundary scan chain around the chip and controls the pin logic such that the boundary scan data controls the data and enable signals for the pins. IEEE 1149.1 requires that an all-zero instruction access the boundary scan chain; the controller actually catches the all-zero condition during the “UpdateIR” state and loads 1FFFFE8h into the internal instruction register.
PAGE 536
33234H GeodeLink™ Control Processor CPU Core GLCP_SYS_RSTPLL[11] PCI Dividers SYSREF SYSPLL GL Clocks SDRAM Clocks GLCP_SYS_RSTPLL[12] DOTREF DOTCLK DOTPLL GLCP_DOTPLL[15] Figure 6-56. Processor Clock Generation 6.13.4 Companion Device Interface The AMD Geode companion device interface for I/O connections (GIO) provides the system interface between the AMD Geode CS5536 companion device and the AMD Geode LX processor.
PAGE 537
33234H IGNNE# GLIU Slave I/F FERR GeodeLink™ Control Processor IRQ13_GL CLK LGCY_GL SMI_GL GIO_GLIU GL Clock Control GIO_SYNC PCI_RAW_CLK GIO_A20M GIO_NMI GIO_SUSP GIO_INIT GIO_INPUT_DIS GIO_OUTPUT_DIS GIO_INTR RQ13 SUSPA# GIO_PCI SUSP# / CIS GLCP_SUSPA Figure 6-57. GIO Interface Block Diagram Table 6-83.
PAGE 538
33234H GIO_PCI Serial Protocol The GIO can override the functionality of its SUSP# pin to create a serial bus called CPU Interface Serial (CIS). The reset mode for this pin is the SUSP# function. To properly operate as the CIS interface, the CISM bit in MSR 51000010h[4:3] in the companion device must be programmed for Mode C. Notice that all the input signals are active low. They are all inverted inside the GIO and converted to active high signals. The protocol is shown in Table 6-84.
PAGE 539
33234H GeodeLink™ Control Processor Register Descriptions 6.14 GeodeLink™ Control Processor Register Descriptions All GeodeLink Control Processor registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instructions. tables that include reset values and page references where the bit descriptions are provided. Note: The registers associated with the GLCP are the Standard GeodeLink™ Device (GLD) MSRs and GLCP Specific MSRs.
PAGE 540
33234H GeodeLink™ Control Processor Register Descriptions Table 6-86.
PAGE 541
33234H GeodeLink™ Control Processor Register Descriptions 6.14.1 Standard GeodeLink™ Device MSRs 6.14.1.
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33234H GeodeLink™ Control Processor Register Descriptions 6.14.1.
PAGE 543
33234H GeodeLink™ Control Processor Register Descriptions 6.14.1.
PAGE 544
33234H GeodeLink™ Control Processor Register Descriptions 6.14.1.5 GLD Power Management MSR (GLD_MSR_PM) MSR Address 4C002004h Type R/W Reset Value 00000000_00000015h The debug logic powers up selecting GLIU1 for its clock. Debug clock select is in GLCP_DBGCLKCTL (MSR 4C000016h[2:0]).
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33234H GeodeLink™ Control Processor Register Descriptions 6.14.2 GLCP Specific MSRs - GLCP Control MSRs 6.14.2.
PAGE 546
33234H GeodeLink™ Control Processor Register Descriptions GLCP_PMCLKDISABLE Bit Descriptions (Continued) 546 Bit Name Description 28 GLCPDBG GLCP Debug Clock Off. When set, disables GLCP DBG logic clock. 27 GLCPGLIU GLCP GLIU Clock Off. When set, disables GLCP GLIU clock. 26 GLCPPCI GLCP GIO PCI Clock Off. When set, disables GLCP’s GIO PCI clock. 25 VPVOP VP VOP Clock Off. When set, disables VOP logic clock. 24 VPDOT_2 VP Dot Clock 2 Off. When set, disables VP Dot Clock 2 (vp_vid).
PAGE 547
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.3 Chip Fabrication Information (GLCP_FAB) MSR Address 4C00000Ah Type RO Reset Value 00000000_00000001h This read only register is used to track various fab, process, and product family parameters. It is meant for AMD internal use only. Reads return reset value. 6.14.2.
PAGE 548
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.5 GLCP Debug Output from Chip (GLCP_DBGOUT) MSR Address 4C00000Ch Type R/W Reset Value 00000000 00000000h This register is reserved for internal use by AMD and should not be written to. 6.14.2.6 GLCP Processor Status (GLCP_PROCSTAT) MSR Address 4C00000Dh Type R/W Reset Value Bootstrap Dependant Note that the names of these bits have the read status data before the "_" and the write behavior after it.
PAGE 549
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.7 GLCP DOWSER (GLCP_DOWSER) MSR Address 4C00000Eh Type R/W Reset Value 00000000_00000000h GLCP_DOWSER Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 SW Defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SW Defined GLCP_DOWSER Bit Descriptions Bit 63:0 Name Description --- Software Defined.
PAGE 550
33234H GeodeLink™ Control Processor Register Descriptions GLCP_DELAY_CONTROLS Bit Definition (Continued) Bit Name Description 59 SDCLK_SET SDCLK Setup. 0: Full SDCLK setup. 1: Half SDCLK setup for control signals. 58:56 55 DDR_RLE SDCLK_DIS DDR read latch enable position. SDCLK disable [1,3,5]. 0: All SDCLK output. 1: SDCLK[4,2,0] output only. 54:52 TLA1_OA TLA hint pin output adjust. 51:50 D_TLA1 Output delay for TLA1. 49:48 D_TLA0 Output delay for TLA0.
PAGE 551
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.9 GLCP Clock Control (GLCP_CLKOFF) MSR Address 4C000010h Type R/W Reset Value 00000000_00000000h This register has bits that, when set, force clocks off using GeodeLink™ Clock Control (GLCC) logic in the system. This is for debugging only, and should not be used for power management.
PAGE 552
33234H GeodeLink™ Control Processor Register Descriptions GLCP_CLKOFF Bit Descriptions (Continued) Bit Name Description 11 DCDOT_0 DC Dot Clock Off. When set, disables DC Dot Clock 0 (DC). 10 GLIU0_1 GLIU0Clock Off. When set, disables main clock to primary GLIU. 9 GLIU0_0 GLIU0 Timer Logic Clock Off. When set, disables clock to timer logic of primary GLIU. 8 GP GP Clock Off. When set, disables GP clock (GLIU). 7 GLMC GLMC Clock Off. When set, disables GLIU clock to memory controller.
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33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.
PAGE 554
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.13 GLCP System Reset and PLL Control (GLCP_SYS_RSTPLL) MSR Address 4C000014h Type R/W Reset Value Bootstrap specific This register is initialized during POR, but otherwise is not itself reset by any “soft-reset” features. Note that writing this register always has immediate effect, so read-modify-writes must be done to avoid corrupting the PLL timing settings.
PAGE 555
GeodeLink™ Control Processor Register Descriptions 33234H GLCP_SYS_RSTPLL Bit Descriptions (Continued) Bit 23:16 Name Description HOLD_COUNT Hold Count. The number of PLL reference clock cycles (divided by 16) that the PLL is powered down for, and also the number before releasing CHIP_RESET. 0: Wait 0 cycles. (Default) 1: Wait 16 clock cycles, etc. 15 RSVD Reserved. Always write 0. 14 GLIUPD GLIU Power Down. This signal controls the power down mode of the GLIU PLL. It is active high.
PAGE 556
33234H GeodeLink™ Control Processor Register Descriptions The PW1 pin (66 MHz PCI) is wired directly to the COREDIV and GLDIV signals during reset. The IRQ13 pin (stall after reset) has no effect on the PLL controls but is still stored in the BOOTSTRAP bits (MSR 4C000018h[7:1]). Table 6-87 shows examples of reset values when PW1 and/or IRQ13 are high during reset. The hard reset state of this register always leaves the PLL in bypass mode.
PAGE 557
33234H GeodeLink™ Control Processor Register Descriptions Table 6-88. Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 vary) {PW1,IRQ13,PW0,SUSPA#,GNT#[2:0]} same as GLCP_SYS_RSTPLL[7:1] CPU Speed CORE MULT GLIU Speed GLIU MULT GLCP_SYS_RSTPLL Reset Value 0100000 Bypass 11 Bypass 7 00000396_00001840h 1000001 166 4 166 4 00000249_03000082h 1110111 500 14 400 11 000005DD_030000EEh 6.14.2.
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33234H GeodeLink™ Control Processor Register Descriptions GLCP_DOTPLL Bit Descriptions Bit Name Description 63:49 RSVD Reserved. Write as read. 48 DIV4 Divide by 4. When set, the PLL output is divided by 4 before clocking the logic. This bit is intended for generating frequencies below the PLL spec limit of 15 MHz. 47 RSVD Reserved. 46:44 MDIV Input Clock Divisor. The DOTPLL M setting (resets to VGA timing). 43:36 NDIV Dot Clock PLL Divisor. The DOTPLL N setting (resets to VGA timing).
PAGE 559
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.15 GLCP Debug Clock Control (GLCP_DBGCLKCTL) MSR Address 4C000016h Type R/W Reset Value 00000000_00000002h Note that after the mux to select the clock, a standard clock control gate exists. This register should never be changed from one non-zero value to another. Always write this register to 0 when moving to an alternative debug clock.
PAGE 560
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.17 GLCP Control (GLCP_CNT) MSR Address 4C000018h Type R/W - I/O Offset 00h Reset Value 00000000_000000Fh This register is used in conjunction with GLIU1 Power Management. I/O writes, which include the lowest byte of this register, may trigger an SMI if GLD_MSR_SMI (MSR 4C002002h) is configured appropriately. MSR writes do not cause SMIs.
PAGE 561
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.
PAGE 562
33234H GeodeLink™ Control Processor Register Descriptions 6.14.2.
PAGE 563
33234H GeodeLink™ Control Processor Register Descriptions 6.14.4 GLCP Specific MSRs - GLCP Debug Interface MSRs 6.14.4.1 GLCP DAC (GLCP_DAC) MSR Address 4C000023h Type R/W Reset Value 00000000_00000000h This register has DAC diagnostic controls and status. It ties directly to inputs and outputs on the DAC module. Bits [13:11] of this register are only valid after the DAC is enabled.
PAGE 564
33234H 6.14.5 GeodeLink™ Control Processor Register Descriptions GLCP Specific MSRs - GLCP Companion Device Interface MSRs 6.14.5.
PAGE 565
33234H GeodeLink™ Control Processor Register Descriptions 6.14.5.3 GLIU Device Interrupt Status (MSR_INTAX) MSR Address 4C000036h Type RO Reset Value 00000000_00000000h This is a read only MSR with the status of interrupt signals from the various blocks. This register is intended for debug purposes. For functional interrupt handlers, the block-specific interrupt registers are memory-mapped. For devices that do not support interrupts, the associated bit is 0.
PAGE 566
33234H 6.15 GeodeLink™ PCI Bridge GeodeLink™ PCI Bridge The GeodeLink™ PCI Bridge (GLPCI) module provides a PCI interface for GeodeLink Interface Unit-based designs. The GLPCI module is composed of five major blocks: Features • PCI Version 2.
PAGE 567
33234H GeodeLink™ PCI Bridge 6.15.1 GeodeLink™ Interface Block The GeodeLink Interface block provides a thin protocol conversion layer between the Transaction Forwarding block and GeodeLink Interface Unit 1 (GLIU1). It is responsible for multiplexing in-bound write request data with out-bound read response data on the single GLIU1 data out bus. 6.15.2 FIFO/Synchronization Block The FIFO module consists of a collection of in-bound and out-bound FIFOs.
PAGE 568
33234H GeodeLink™ PCI Bridge AMD Geode™ LX Processor CPU Core GLPCI_EXT (MSR 5000201Eh) configuration: GLIU-port1 -> PCI-device-15 GLIU-port2 -> PCI-device-25 GLIU-port3 -> PCI-device-30 GLIU-port4 -> PCI-device-1 GLIU0 2 GLIU1 4 GLPCI PCI-device = 1 PCI-device = 15 PCI-device = 25 PCI-device = 30 GLPCI GLPCI GLPCI GLIU0 GLIU0 GLIU0 3 5 2 GLIU1 GLIU1 GLIU1 6 1 7 Device-A Device-B 2.4.1.3.6.x 2.4.2.5.1.x GLIU2 3 Device-C 2.4.3.2.7.3 Figure 6-59.
PAGE 569
33234H GeodeLink™ PCI Bridge 6.15.4 PCI Bus Interface Block 6.15.4.1 The PCI Bus Interface block is compliant to the PCI 2.2 specification, except in the handling of SERR#/PERR# signals. These signals are not available. The PCI Bus Interface block provides a protocol conversion layer between the Transaction Forwarding block and the PCI bus. The master and target portions of this block operate independently.
PAGE 570
33234H GeodeLink™ PCI Bridge Table 6-90. PCI Device to AD Bus Mapping PCI Device AD Pin PCI Device AD Pin PCI Device AD Pin PCI Device AD Pin 0 N/A 8 18 16 26 24 N/A 1 11 9 19 17 27 25 N/A 2 12 10 20 18 28 26 N/A 3 13 11 21 19 29 27 N/A 4 14 12 22 20 30 28 N/A 5 15 13 23 21 31 29 N/A 6 16 14 24 22 N/A 30 N/A 7 17 15 25 23 N/A 31 N/A 6.15.
PAGE 571
GeodeLink™ PCI Bridge 6.15.6 Exception Handling 6.15.6.1 Out-Bound Write Exceptions When performing an out-bound write on the PCI bus, two errors may occur: target abort and PERR# assertion. When a target abort occurs, the PCI Bus Interface block must flush any stored write data. It must then report the error. The assertion of PERR# is handled generically. The failed transaction will not be retried. 6.15.6.
PAGE 572
33234H 6.16 GeodeLink™ PCI Bridge Register Descriptions GeodeLink™ PCI Bridge Register Descriptions All GeodeLink™ PCI Bridge (GLPCI) registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instructions. The registers associated with the GLPCI are the Standard GeodeLink Device (GLD) MSRs and GLPCI Specific MSRs. Table 6-91 and Table 6-92 are register summary tables that include reset values and page references where the bit descriptions are provided.
PAGE 573
33234H GeodeLink™ PCI Bridge Register Descriptions Table 6-92.
PAGE 574
33234H 6.16.1 GeodeLink™ PCI Bridge Register Descriptions Standard GeodeLink™ Device (GLD) MSRs 6.16.1.
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33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.1.
PAGE 576
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.1.
PAGE 577
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.1.5 GLD Power Management MSR (GLD_MSR_PM) MSR Address 50002004h Type R/W Reset Value 00000000_00000015h GLD_MSR_PM Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 6 5 4 3 2 1 0 PM0 7 PM1 RSVD 8 RSVD 9 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PM2 RSVD GLD_MSR_PM Bit Descriptions Bit 63:5 4 Name Description RSVD (RO) Reserved (Read Only).
PAGE 578
33234H 6.16.2 GeodeLink™ PCI Bridge Register Descriptions GLPCI Specific Registers 6.16.2.
PAGE 579
33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_CTRL Bit Descriptions (Continued) Bit Name Description 42 SLTO Subsequent Latency Timeout Select. Specifies the subsequent target latency timeout limit. If within a burst, the GLPCI module does not respond with the configured number of clock ticks, the PCI interface will terminate the PCI bus cycle. 0: 8 PCI clock edges 1: 4 PCI clock edges 41:40 ILTO Initial Latency Timeout Select.
PAGE 580
33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_CTRL Bit Descriptions (Continued) Bit Name Description 24 MARS Master Abort Receive ASMI. Allow reception of a PCI bus master abort to be reported in the TARE bit (MSR 50002002h[17]). 0: Disable. 1: Enable. 23:21 SUS Busy Sustain. Controls the sustain time for keeping the clocks running after the internal busy signals indicate that the clocks may be gated.
PAGE 581
33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_CTRL Bit Descriptions (Continued) Bit Name Description 9 LDE Latency Disconnect Enable. Writing 1, causes the PCI interface to disconnect from a PCI bus master when a latency timer expiration occurs. This enforces the configured minimum latency upon PCI bus masters where the GLPCI module is a target on the PCI bus. The latency timer must be greater than 0 when using this feature. 8 RUPO Relax Up-Stream Ordering.
PAGE 582
33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_ARB Bit Definitions Bit Name Description 63:60 CR CPU Repeat. Controls the number of consecutive grants given to the CPU before rotating to the next requestor. This is only valid if there is a non-zero value for the CPU HoldGrant control (CH, bits [47:44]). This may be overidden by either OV2, OV1 or OV0 (bits [22:20]). It is also ignored if the CPRE (bit 11) is cleared. 59:56 R2 Request Repeat 2.
PAGE 583
GeodeLink™ PCI Bridge Register Descriptions 33234H GLPCI_ARB Bit Definitions (Continued) Bit Name Description 20 OV0 Override 0. Enables requester0 to override the repeat-count and grant-hold for other requestors. When OV0 is set and REQ0# is asserted, repeat-count and grant-hold mechanisms for other masters are temporarily disabled. This bit does not change the round robin arbitration cycle, it only overrides repeat-count and grant-hold for other requestors. 19 RSVD (RO) Reserved (Read Only).
PAGE 584
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.3 GLPCI VPH / PCI Configuration Cycle Control (GLPCI_PBUS) MSR Address 50002012h Type R/W Reset Value 00FF0000_00000000h The PBUS model specific register is used to control the way that the GLPCI module generates (or does not generate) PCI configuration cycles onto the PCI bus. SEC (bits [39:32]) should be configured with the PCI bus number for the locally attached PCI bus.
PAGE 585
33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_REN Bit Descriptions Bit Name Description 63:32 Spare Spare Bits. Extra bits available for future use. These bits may be set and cleared, but do not control anything. 31:24 RSVD (RO) Reserved (Read Only). Reserved for future use 23 FC FC Enable. Enables memory access to FC000 through FFFFF from PCI. 22 F8 F8 Enable. Enables memory access to F8000 through FBFFF from PCI. 21 F4 F4 Enable.
PAGE 586
33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_A0 Bit Descriptions Bit Name Description (Note 1) 63:56 BC BC Properties. Region properties for BC000 through BFFFF. 55:48 B8 B8 Properties. Region properties for B8000 through BBFFF. 47:40 B4 B4 Properties. Region Properties for B4000 through B7FFF. 39:32 B0 B0 Properties. Region properties for B0000 through B3FFF. 31:24 AC AC Properties. Region properties for AC000 through AFFFF. 23:16 A8 A8 Properties.
PAGE 587
33234H GeodeLink™ PCI Bridge Register Descriptions GLPCI_C0 Bit Descriptions (Continued) Bit Name Description (Note 1) 39:32 D0 D0 Properties. Region properties for D0000 through D3FFF. 31:24 CC CC Properties. Region properties for CC000 through CFFFF. 23:16 C8 C4 Properties. Region Properties for C8000 through CBFFF. 15:8 C4 C4 Properties. Region Properties for C4000 through C3FFF. 7:0 C0 C0 Properties. Region properties for C0000 through C3FFF. Note 1.
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33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 589
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 590
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 591
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 592
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 593
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 594
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 595
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.16 GLPCI Spare MSR Address 5000201Fh Type R/W Reset Value 00000000_00000003h GLPCI Spare 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 5 4 3 2 1 NSE 0 SUPO 6 MME RSVD 7 MPC 8 PPC Spare 9 PPD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AILTO Spare GLPCI Spare Bit Descriptions Bit Name Description 63:10 Spare Spare Bits.
PAGE 596
33234H GeodeLink™ PCI Bridge Register Descriptions 6.16.2.
PAGE 597
Electrical Specifications 33234H 7 7.0Electrical Specifications This section provides information on electrical connections, absolute maximum ratings, operating conditions, and DC/AC characteristics for the AMD Geode™ LX processor. All voltage values in the electrical specifications are with respect to VSS unless otherwise noted. 7.1 Electrical Connections 7.1.
PAGE 598
33234H 7.3 Electrical Specifications Operating Conditions Table 7-2 lists the operating conditions for the AMD Geode LX processor. Table 7-2. Operating Conditions Symbol Parameter (Note 1) TC Operating Case Temperature LX 900@1.5W Operating Case Temperature LX 800@0.9W Operating Case Temperature LX 700@0.8W LX 600@0.7W VCORE Min Typ 0 Max Unit 80 °C 0 85 °C -40 85 °C 0 85 °C Comments See Section A.1 "Order Information" for applicable OPN. Core Supply Voltage LX 900@1.5W 1.36 1.
PAGE 599
33234H Electrical Specifications 7.4 DC Current DC current is not a simple measurement. Three of the AMD Geode LX processor’s power states (ON, Active Idle, and Sleep) were selected for measurement. For the ON power state measured, two functional characteristics (Typical Average and Absolute Maximum) are used to determine how much current the processor requires. 7.4.1 Power State Parameter Definitions The DC current tables in this section list Core and I/O current for three of the power states.
PAGE 600
33234H Electrical Specifications The data bus on the DDR SDRAM has a low voltage swing when actively terminated (terminated topology). The terminated topology supports higher data transfer rates and is less constrained, but it consumes more power. Many designs should be able to operate reliably without active termination (unterminated topology). The design constraints are smaller memory subsystems and tight control on routing.
PAGE 601
33234H Electrical Specifications Table 7-4. AMD Geode LX 800@0.9W Processor DC Currents LX 800@0.9W (500 MHz), No EEPROM, VCORE = 1.25V, TDPT = 3.8W, TDPU = 3.
PAGE 602
33234H Electrical Specifications Table 7-5. AMD Geode LX 700@0.8W Processor DC Currents LX 700@0.8W (433 MHz), No EEPROM or EEPROM, VCORE = 1.20V, TDPT = 3.2W, TDPU = 3.
PAGE 603
33234H Electrical Specifications Table 7-6. AMD Geode LX 600@0.7W Processor DC Currents LX 600@0.7W (366 MHz), No EEPROM, VCORE = 1.20V, TDPT = 2.9W, TDPU = 2.
PAGE 604
33234H 7.5 Electrical Specifications DC Characteristics All DC parameters and current measurements in this section were measured under the operating conditions listed in Table 7-2 "Operating Conditions", unless otherwise noted. The signals associated with the seven signal buffer types on the AMD Geode LX processor, are shown Table 3-5 "Ball Assignments - Sorted by Ball Number" on page 26. Table 7-7.
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33234H Electrical Specifications Table 7-7. DC Characteristics (Continued) Symbol Parameter Min Max ILEAK Input Leakage Current Including Hi-Z Output Leakage, Note 1 Units PCI -3.0 3.0 µA 24/Q3 -3.0 3.0 µA 24/Q5 -3.0 3.0 µA 24/Q7 -3.0 3.0 µA 5V -3.0 3.0 µA Comments If VIH > VIO, ILEAK max = 20 µA IPU/PD DDR -3.0 3.0 µA DDRCLK -5.0 5.
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33234H Electrical Specifications Table 7-7. DC Characteristics (Continued) Symbol Parameter IOL Output Low Current, Note 1 Max Units Comments VO = VOL (Max) PCI 1500 µA 24/Q3 24.0 mA 24/Q5 24.0 mA 24/Q7 24.0 mA 5V 16.0 mA DDR (BA[1:0], MA[13:0]) 15.2 mA IOL min = 11 mA with halfdrive set for pad 11 mA IOL min = 8 mA with quarterdrive set for pad 10.
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33234H Electrical Specifications 7.6 AC Characteristics The following tables list the AC characteristics including output delays, input setup requirements, input hold requirements, and output float delays. The rising-clock-edge reference level VREF, and other reference levels are shown in Figure 7-2. Input or output signals must cross these levels during testing.
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33234H Electrical Specifications Table 7-8. System Interface Signals Symbol Parameter Min Max Unit tCK SYSREF Cycle time 15.0 INF ns 66 MHz tCH SYSREF High time 6.0 ns 40% tCK tCL SYSREF Low time 6.0 ns 40% tCK tSU1 RESET# Setup time to SYSREF 3 ns Note 1 tH1 RESET# Hold time from SYSREF 1 ns Note 1 tSU2 CIS Setup time to SYSREF 3.0 ns tH2 CIS Hold time from SYSREF 0 ns tVAL1 IRQ13 Valid Delay time from SYSREF 2.0 6.
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33234H Electrical Specifications VCORE tON VIO,VMEM tMVON MVREF SYSREF cycle time not to scale with other delays in this figure. tRSTX SYSREF RESET# tZ Outputs Figure 7-4. Power Up Sequencing Table 7-9. PCI Interface Signals Symbol Parameter Min Max Unit Comments tSU1 Input Setup time to SYSREF 3.0 ns 4.
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33234H Electrical Specifications Table 7-10. VIP Interface Signals Symbol Parameter Min tCK VIPCLK period 12.5 ns 80 MHz tCH VIPCLK High time 3.0 ns 45% tCK tCL VIPCLK Low time 3.0 ns 45% tCK tVAL VIP_SYNC Output Valid Delay time from VIPCLK 1.0 tSU1 VID[7:0] Input Setup time to VIPCLK 2.0 ns tH1 VID[7:0] Input Hold time from VIPCLK. 0.2 ns tCH Max 4.
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33234H Electrical Specifications Table 7-11. Flat Panel Interface Signals Symbol Parameter Min Max tCK DOTCLK period 6.0 ns 166 MHz tCH DOTCLK High time 2.7 ns 45% tCK tCL DOTCLK Low time 2.7 ns 45% tCK DOTCLK long term output jitter 15% Unit tCK tVAL1 DRGB[31:0] Output Valid Delay time from rising edge of DOTCLK 0.5 3.0 ns tVAL2 DISPEN, LDEMOD Output Valid Delay time from rising edge of DOTCLK 0.5 3.
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33234H Electrical Specifications Table 7-12. CRT Interface Signals Symbol Parameter Min Max tCK DOTCLK Period 2.8 ns 350 MHz tCH DOTCLK High time 1.2 ns 45% tCK tCL DOTCLK Low time 1.2 ns 45% tCK DOTCLK long term output jitter tSKEW 15% Skew between RED, GREEN, BLUE Output Valid 0 Unit tCK 0.6 ns Comments Note 1 Between any two signals Note 2 Note 1. Measured as per VESA requirements.
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33234H Electrical Specifications Table 7-14. CRT Display Analog (DAC) Characteristics Symbol Parameter Min Typ Max Units VOS Output Voltage Saturation Limit 1.25 IOVAR Output Current INL Integral Linearity Error +/-1 LSB DNL Differential Linearity Error +/-1 LSB tFS Full Scale Settling Time 2.5 ns -- DAC-to-DAC matching 1 4 % -- Analog Power Supply Rejection 45 tRISE Output Rise Time 0.5 tFALL Output Fall Time 0.5 Comments (Note 1) V 18.67 mA Achieves 700 mV on 37.
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33234H Electrical Specifications Table 7-15. Memory (DDR) Interface Signals Symbol (Note 1) Parameter Min tCK SDCLK[5:0]P, SDCLK[5:0]N period 5.0 ns Note 2 tCH SDCLK[5:0]P, SDCLK[5:0]N High time 2.4 ns 48% tCK tCL SDCLK[5:0]P, SDCLK[5:0]N Low time 2.4 ns 48% tCK tSKEW1 SDCLK[n]P to SDCLK[n]N skew (n=0..5) 0.1 ns Guaranteed by design tDEL1 SDCLK[5:1]P, SDCLK[5:0]N edge delay from SDCLK[0]P -0.2 0.2 ns Note 2, Note 3 DQS[7:0] Input and output period 5.
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33234H Electrical Specifications SDCLK0P VREF SDCLK[5:1]P VREF tDEL1 tSKEW1 tSKEW1 VREF SDCLK[5:0]N tDEL2 VIHD DQS Outputs VILD VREF tVAL2Max tVAL2Min Valid Output n Non-DQ Outputs DQS Valid Output n+1 VREF VIHD VILD VREF tVAL1Max tVAL1Min DQ n DQ Outputs DQ n+1 DQ n+2 VREF Figure 7-8.
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33234H Electrical Specifications VREF SDCLK0 tDQSCKMax VREF DQS ‘Late’ Input tDQSCKMin VREF DQS ‘Early’ Input VREF DQS[n] Input tSKEW2 tSKEW2 VREF other DQS Input tDQSQh DQ Inputs associated with DQS[n] -tDQSQs DQt-1 DQt DQt+1 DQt+2 VREF Figure 7-9.
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33234H Electrical Specifications Table 7-16. JTAG Interface Signals Symbol Parameter Max Unit Comments TCLK period 15 ns Note 1 TCLK High time 4 ns 40% period TCLK Low time 4 ns 40% period TDI, TMS Setup time to TCLK rising edge 1.5 ns TMS Hold time from TCLK rising edge 3.0 ns TDI Hold time from TCLK rising edge - Boundary scan 3.
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33234H 618 Electrical Specifications AMD Geode™ LX Processors Data Book
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Instruction Set 33234H 8 8.0Instruction Set This chapter provides the general instruction set format and detailed information on the AMD Geode™ LX processor’s instructions/instruction encodings. The instruction set is divided into three categories: • CPUID Instruction Set - listed in Section 8.2 on page 627. • Processor Core Instruction Set - listed in Section 8.3 on page 633. • MMX™, FPU, and AMD 3DNow!™ Instruction Sets (including extensions) - listed in Section 8.4 on page 658.
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33234H Instruction Set Table 8-2. Instruction Fields Field Name Description Prefix (optional) Prefix Field(s): One or more optional fields that are used to specify segment register override, address and operand size, repeat elements in string instruction, and LOCK# assertion. Opcode Opcode Field: Identifies instruction operation. mod Address Mode Specifier: Used with the r/m field to select addressing mode.
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33234H Instruction Set 8.1.2 Opcode The opcode field specifies the operation to be performed by the instruction. The opcode field is either one or two bytes in length and may be further defined by additional bits in the mod r/m byte. Some operations have more than one opcode, each specifying a different form of the operation. Certain opcodes name instruction groups. For example, opcode 80h names a group of operations that have an immediate operand and a register or memory operand.
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33234H Instruction Set 8.1.2.4 eee Field (MOV-Instruction Register Selection) The eee field (bits [5:3]) is used to select the control, debug, and test registers in the MOV instructions. The type of register and base registers selected by the eee field are listed in Table 8-7. The values shown in Table 8-7 are the only valid encodings for the eee bits. Table 8-7. eee Field Encoding 8.1.
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33234H Instruction Set Table 8-8.
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33234H 8.1.4 Instruction Set reg Field The reg field (Table 8-10) determines which general registers are to be used. The selected register is dependent on whether a 16-bit or 32-bit operation is current and on the status of the w bit. Table 8-10. reg Field 16-Bit Operation 32-Bit Operation reg w=0 w=1 w=0 w=1 000 AL AX AL EAX 001 CL CX CL ECX 010 DL DX DL EDX 011 BL BX BL EBX 100 AH SP AH ESP 101 CH BP CH EBP 110 DH SI DH ESI 111 BH DI BH EDI 8.1.4.
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33234H Instruction Set 8.1.5 s-i-b Byte (Scale, Indexing, Base) The s-i-b fields provide scale factor, indexing, and a base field for address selection. The ss, index, and base fields are described next. 8.1.5.1 ss Field (Scale Selection) The ss field (Table 8-13) specifies the scale factor used in the offset mechanism for address calculation. The scale factor multiplies the index value to provide one of the components used to calculate the offset address. Table 8-13.
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33234H Instruction Set 8.1.5.3 Base Field (s-i-b Present) In Table 8-8 on page 622, the note “s-i-b is present” for certain entries forces the use of the mod and base field as listed in Table 8-15. The first two digits in the first column of Table 8-15 identify the mod bits in the mod r/m byte. The last three digits in the second column of this table identify the base fields in the s-i-b byte. Table 8-15.
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33234H Instruction Set 8.2 CPUID Instruction Set The CPUID instruction (opcode 0FA2) allows software to make processor inquiries as to the vendor, family, model, stepping, features, and specific cache organization information. The presence of support for the CPUID instruction is indicated by the ability to change the value of the ID flag, bit 21, in the EFLAGS register. The CPUID level allows the CPUID instruction to return different information in EAX, EBX, ECX, and EDX registers.
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33234H Instruction Set Table 8-18.
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33234H Instruction Set Table 8-18. CPUID Instruction Codes with EAX = 00000000 Register Reset Value Description Comment Not supported EDX[1] 0 VME. Virtual Interrupt Flag in VM86 EDX[0] 1 FPU. Floating Point Unit On Chip 8.2.2 Extended CPUID Levels Testing for extended CPUID instruction support can be accomplished by executing a CPUID instruction with the EAX register initialized to 80000000h.
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33234H Instruction Set Table 8-21. CPUID Instruction Codes with EAX = 80000001h Register Reset Value Description EAX[31:28] 0x0 Reserved EAX[27:20] 0x00 Extended Family EAX[19:16] 0x00 Extended Model EAX[15:12] 0x0 Reserved EAX[11:8] 0x5 Processor/Instruction Family EAX[7:4] 0x5 Processor Model EAX[3:0] 0x2 Processor Stepping EDX[31] 1 3DN. 3DNow! Instruction Set EDX[30] 1 3DE.
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33234H Instruction Set 8.2.2.3 CPUID Instruction with EAX = 80000002h, 80000003h, or 80000004h Extended functions 80000002h through 80000004h (EAX = 80000002h, EAX = 80000003h, and EAX = 80000004h) of the CPUID instruction returns an ASCII string containing the CPU marketing name, as shown in Table 8-22. These functions eliminate the need to look up the processor name in a lookup table. Software can simply call these functions to obtain the name of the processor.
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33234H Instruction Set 8.2.2.4 CPUID Instruction with EAX = 80000005h Extended function 80000005h (EAX = 80000005h) of the CPUID instruction returns information on the internal L1 cache and TLB structures. They are used for reporting purposes only. See Table 8-23 for returned contents. 8.2.2.5 CPUID Instruction with EAX = 80000006h Extended function 80000006h (EAX = 80000006h) of the CPUID instruction returns information on the internal L2 cache and TLB structures.
PAGE 633
33234H Instruction Set 8.3 Processor Core Instruction Set The instruction set for the AMD Geode LX processor core is summarized in Table 8-26. The table uses several symbols and abbreviations that are described next and listed in Table 8-25. 8.3.1 Opcodes Opcodes are given as hex values except when they appear within brackets as binary values. 8.3.
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33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
PAGE 636
33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
PAGE 640
33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
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33234H Instruction Set Table 8-26.
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Instruction Set 33234H Instruction Notes for Instruction Set Summary Notes a through c apply to real address mode only: a. This is a protected mode instruction. Attempted execution in real mode results in exception 6 (invalid opcode). b. Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, DS, ES, FS, or GS segment limit.
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33234H Instruction Set 8.3.4 Non-Standard Processor Core Instructions 8.3.4.
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33234H Instruction Set Description The DMINT instruction saves portions of the processors state to the Debug Management Mode (DMM) header, alters the processors state for DMM, enters DMM, and then calls the DMM mode handler. Below is the format of the DMM header.
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33234H 8.3.4.
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33234H Instruction Set 8.3.4.4 RDM - Leave Debug Management Mode Opcode Instruction Clocks Description 0F 3A RDM 36 Return from DMI Operation IF (CPL<>0 OR (DMM_INST_EN=0 AND SMM=0 AND DMM=0)) #UD; ELSE DR6 <= DMM_HEADR[DR6]; DR7 <= DMM_HEADER[DR7]; XDR6 <= DMM_HEADER[XDR6]; XDR7 <= DMM_HEADER[XDR7]; SS.FLAGS <= DMM_HEADER[SS.FLAGS]; SS.SELECTOR <= DMM_HEADER[SS.SELECTOR]; CPL <= DMM_HEADER[SS.DPL] CS.FLAGS <= DMM_HEADER[CS.FLAGS]; CS.SELECTOR <= DMM_HEADER[CS.SELECTOR]; CS.
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33234H Instruction Set Exceptions #UD If current privilege level is not 0, or the DMM_INST_EN = 0 and if the processor is not in SMM and if the processor is not in DMM. Notes Data address breakpoints on DMM header addresses are ignored during the execution of the RSM instruction. The RDM instruction does not check the values that it reads from the DMM header for validity. The RDM instruction sets the current privilege level to the SS DPL value read from the DMM header.
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33234H Instruction Set 8.3.4.6 RSLDT - Restore Local Descriptor Table Register and Descriptor Opcode Instruction Clocks Description 0F 7B RSLDT m80 11 Restore LDTR from memory Operation IF (CPL<>0 OR (SMM_INST_EN=0 AND SMM=0 AND DMM=0)) #UD; ELSE LDT.DESCR <= MEM80; Description Restore the Local Descriptor Table register and descriptor from memory. Below is the format of the descriptor contents in memory.
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33234H 8.3.4.7 Instruction Set RSM - Leave System Management Mode Opcode Instruction Clocks Description 0F AA RSM 36 Return from SMI Operation IF (CPL<>0 OR (SMM_INST_EN=0 AND SMM=0 AND DMM=0)) #UD; ELSE SMM_CTL <= SMM_HEADER[SMM_CTL]; SS.FLAGS <= SMM_HEADER[SS.FLAGS]; CPL <= SMM_HEADER[SS.DPL]; CS.LIMIT <= SMM_HEADER[CS.LIMIT]; CS.BASE <= SMM_HEADER[CS.BASE] CS.SELECTOR <= SMM_HEADER[CS.SELECTOR]; CS.FLAGS <= SMM_HEADER[CS.
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33234H Instruction Set Notes The RSM instruction does not check the values that it reads from the SMM header for validity. The RSM instruction set the current privilege level to the SS DPL value read from the SMM header. If a RSM restores the processor to real mode, the VM bit of the EFlags register is cleared regardless of the state of the VM bit in the EFlags value of the SMM header.
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33234H Instruction Set Exceptions None. Notes None. 8.3.4.10 SMINT - Enter System Management Mode Opcode Instruction Clocks Description 0F 38 SMINT 55 Enter SMM and call the SMI handler Operation IF (CPL<>0 OR (SMM_INST_EN=0 AND SMM=0 AND DMM=0)) #UD; ELSE SMM_HEADER[SMM_CTL] <= SMM_CTL; SMM_HEADER[I/O_DATA] <= 0; SMM_HEADER[I/O_ADDRESS] <= 0; SMM_HEADER[I/O_SIZE] <= 0; SMM_HEADER[SMM_FLAGS] <= SMM_FLAGS; SMM_HEADER[SS_FLAGS] <= SS.FLAGS; SMM_HEADER[CS_LIMIT] <= CS.
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33234H Instruction Set Description The SMINT instruction saves portions of the processors state to the System Management Mode (SMM) header, alters the processors state for SMM, enters SMM, and then calls the SMM handler. Below is the format of the SMM header.
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33234H Instruction Set 8.3.4.12 SVDC - Save Segment Register and Descriptor Opcode Instruction Clocks Description 0F 78 /r SVDC sr, m80 7 Restore descriptor from memory Operation IF (CPL<>0 OR (SMM_INST_EN=0 AND SMM=0 AND DMM=0)) #UD; ELSE MEM80 <= SEG.DESCR; Description Write the specified segment descriptor (either DS, ES, FS, GS, SS, or CS) to memory. Below is the format of the descriptor contents in memory.
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33234H Instruction Set Exceptions #UD If current privilege level is not 0, or the SMM_INST_EN = 0 and if the processor is not in SMM and if the processor is not in DMM. Notes The reg field within the mod r/m byte must be zero for the SVLDT instruction to be recognized. 8.3.4.14 SVTS - Save Task Register and Descriptor Opcode Instruction Clocks Description 0F 7C SVTS m80 8 Save TS to memory Operation IF (CPL<>0 OR (SMM_INST_EN=0 AND SMM=0 AND DMM=0)) #UD; ELSE MEM80 <= TS.
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33234H 8.4 Instruction Set MMX™, FPU, and AMD 3DNow!™ Technology Instructions Sets The CPU is functionally divided into the Floating Point Unit (FPU) unit and the Integer Unit. The FPU has been extended to process MMX, AMD 3DNow!, and floating point instructions in parallel with the Integer Unit. When the Integer Unit detects an MMX instruction, the instruction is passed to the FPU or execution. The Integer Unit continues to execute instructions while the FPU executes the MMX instruction.
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33234H Instruction Set Table 8-27. MMX™, FPU, and AMD 3DNow!™ Instruction Set Table Legend Abbreviation Description windex 1 (imm8) The range given by [index1 (imm8) + 15: index1 (imm8)]. windex 2 (imm8) The range given by [index2 (imm8) + 15: index2 (imm8)]. windex 3 (imm8) The range given by [index3 (imm8) r15: indes3 (imm8)]. windexall (imm8) The four different index # (imm8) ordered in the same way as word.
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33234H Instruction Set Table 8-28.
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33234H Instruction Set Table 8-28.
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33234H Instruction Set Table 8-28.
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33234H Instruction Set Table 8-28.
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33234H Instruction Set Table 8-28.
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33234H Instruction Set Table 8-28.
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33234H Instruction Set Table 8-28. MMX™ Instruction Set (Continued) MMX™ Instructions Opcode Operation Clock Ct Notes PXOR Bitwise XOR MMX Register 2 to MMX Register 1 0FEF [11 mm1 mm2] MMX reg 1 [qword] --- MMX reg 1 [qword], <--- logic exclusive OR MMX reg 2 [qword] 2 Memory to MMX Register 0FEF [11 mm reg] MMX reg [qword] --- memory64 [qword], <--- logic exclusive OR MMX reg [qword] 2 SFENCE Store Fence 0FAE [mod 111 r/m] 1) 666 This instruction must wait for the FPU pipeline to flush.
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33234H Instruction Set Table 8-29. FPU Instruction Set FPU Instruction Opcode Operation TOS Clock Ct Single/Dbl (or extended) Notes 145 - 166 2 1 3 F2XM1 Function Evaluation 2x-1 D9 F0 TOS <--- 2 FABS Floating Absolute Value D9 E1 TOS <--- | TOS | Top of Stack DC [1100 0 n] ST(n) <--- ST(n) + TOS 1/6 80-bit Register D8 [1100 0 n] TOS <--- TOS + ST(n) 1/6 64-bit Real DC [mod 000 r/m] TOS <--- TOS + M.DR 1/6 32-bit Real D8 [mod 000 r/m] TOS <--- TOS + M.
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33234H Instruction Set Table 8-29. FPU Instruction Set (Continued) FPU Instruction FDECSTP Decrement Stack pointer Opcode Operation Clock Ct Single/Dbl (or extended) Notes 1 3 D9 F6 Decrement top of stack pointer Top of Stack DC [1111 1 n] ST(n) <--- ST(n) / TOS 80-bit Register D8 [1111 0 n] TOS <--- TOS / ST(n) 12/47 64-bit Real DC [mod 110 r/m] TOS <--- TOS / M.DR 12/47 FDIV Floating Point Divide 32-bit Real 12/47 D8 [mod 110 r/m] TOS <--- TOS / M.
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33234H Instruction Set Table 8-29. FPU Instruction Set (Continued) FPU Instruction Opcode Operation Clock Ct Single/Dbl (or extended) Notes 3 FPATAN Function Eval: Tan-1(y/x) D9 F3 ST(1) <--- ATAN[ST(1) / TOS]; then pop TOS 269 - 354 FPREM Floating Point Remainder D9 F8 TOS <--- Rem[TOS / ST(1)] 53 - 208 FPREM1 Floating Point Remainder IEEE D9 F5 TOS <--- Rem[TOS / ST(1)] 53 - 208 FPTAN Function Eval: Tan(x) D9 F2 TOS <--- TAN(TOS); then push 1.
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33234H Instruction Set Table 8-29. FPU Instruction Set (Continued) FPU Instruction Opcode Operation Clock Ct Single/Dbl (or extended) Notes FISUB Floating Point Integer Subtract 32-bit Integer DA [mod 100 r/m] TOS <--- TOS - M.SI 2/7 16-bit Integer DE [mod 100 r/m] TOS <--- TOS - M.WI 2/7 FISUBR Floating Point Integer Subtract Reverse 32-bit Integer Reversed DA [mod 101 r/m] TOS <--- M.SI - TOS 2/7 16-bit Integer Reversed DE [mod 101 r/m] TOS <--- M.
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33234H Instruction Set Table 8-30.
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33234H Instruction Set Table 8-30.
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33234H Instruction Set Table 8-30.
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33234H Instruction Set 8.4.1 Non-Standard AMD 3DNow!™ Technology Instructions 8.4.1.
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Package Specifications 33234H 9 9.0Package Specifications 9.1 Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 (481-terminal Ball Grid Array Cavity Up) Figure 9-1.
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33234H Package Specifications Figure 9-2.
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Appendix A: Support Documentation 33234H A Appendix ASupport Documentation A.1 Order Information Ordering information for the AMD Geode™ LX processors is contained in this section. The ordering part number (OPN) is formed by a combination of elements. An example of the OPN is shown in Figure A-1. Valid OPN combinations are provided in Table A-1 on page 678.
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33234H Appendix A: Order Information Table A-1. Valid OPN Combinations Family Architecture MTDP Performance Indicator Package Type Operating Voltage System Bus Speed EEPROM Indicator Display Type Case Temperature/ Solder Type (Note) ALX G 900 EE Y J 2 V H ALX D 800 EE X J 2 V C D F C C D ALX C 700 EE T H 2 V C D C C D ALX Note: C 600 EE T K 2 V D θJC = 3.
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33234H Appendix A: Data Book Revision History A.2 Data Book Revision History This document is a report of the revision/creation process of the data book for the AMD Geode™ LX processors. Any revision (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below. Table A-2. Revision History Revision # (PDF Date) 0.1 (April 2004) 0.5 (September 2004) 0.9 (January 2005) A (May 2005) B (October 2005) Revisions / Comments Advance Information.
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