Specifications

Product Errata 89
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
25759 Rev. 3.79 July 2009
Dev:0x90h, B0h, D0h LDT Buffer Count Register Settings for Inner Nodes
Dev:3x70h SRI to XBAR Buffer Count Register Settings for Inner Nodes
Dev:3x78h MCT to XBAR Buffer Count Register Settings for Inner Nodes
Fix Planned
Yes
Mnemonic Req Preq Rsp Probe
Register Bits [3:0] [7:4] [11:8] [15:12]
Coherent links 2 1 5 4
Mnemonic DReq DPReq UReq UPReq URsp
Register Bits [29:28] [31:30] [1:0] [5:4] [9:8]
Value 0 0 1 1 1
Mnemonic Rsp Prb
Register Bits [11:8] [14:12]
Value 5 2