Specifications

88 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
Dev:0x90h, B0h, D0h LDT Buffer Count Register Settings for Outer Nodes
Dev:3x70h SRI to XBAR Buffer Count Register Settings for Outer Nodes
Dev:3x78h MCT to XBAR Buffer Count Register Settings for Outer Nodes
Inner Node Virtual Channel Command Buffer Allocation
Total Command Buffer Allocation Per Inner Node
Mnemonic Req PReq Rsp Probe
Register Bits [3:0] [7:4] [11:8] [15:12]
Coherent Links 1 1 6 4
Non-Coherent Links 5 4 1 0
Mnemonic DReq DPReq UReq UPReq URsp
Register Bits [29:28] [31:30] [1:0] [5:4] [9:8]
Value 11111
Mnemonic Rsp Prb
Register Bits [11:8] [14:12]
Value 5 2
Link Request
Posted
Request
Response Probe
Number of
Command Buffers
Coherent links 2 1 5 4 12
SRI 1 2 3 0 6
MCT 0 0 5 2 7
Allocation Inner Node
12 Coherent link
12 Coherent link
12 Coherent link
6 SRI (includes three buffers from FreeList Buffer Count
register)
7MCT
49 Total