Specifications

86 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
147 Potential Violation of Read Ordering Rules Between
Semaphore Operations and Unlocked Read-Modify-Write
Instructions
Description
Under a highly specific set of internal timing circumstances, the memory read ordering between a
semaphore operation and a subsequent read-modify-write instruction (an instruction that uses the
same memory location as both a source and destination) may be incorrect and allow the read-modify-
write instruction to operate on the memory location ahead of the completion of the semaphore
operation. The erratum will not occur if there is a LOCK prefix on the read-modify-write instruction.
This erratum does not apply if the read-only value in MSRC001_1023h[33] is 1b.
Potential Effect on System
In the unlikely event that the condition described above occurs, the read-modify-write instruction (in
the critical section) may operate on data that existed prior to the semaphore operation. This erratum
can only occur in multiprocessor or multicore configurations.
Suggested Workaround
To provide a workaround for this unlikely event, software can perform any of the following actions
for multiprocessor or multicore systems:
• Place a LFENCE instruction between the semaphore operation and any subsequent read-modify-
write instruction(s) in the critical section.
• Use a LOCK prefix with the read-modify-write instruction.
• Decompose the read-modify-write instruction into separate instructions.
No workaround is necessary if software checks that MSRC001_1023h[33] is set on all processors that
may execute the code. The value in MSRC001_1023h[33] may not be the same on all processors in a
multi-processor system.
Fix Planned
Yes