Specifications

80 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
122 TLB Flush Filter May Cause Coherency Problem in Multicore
Systems
Description
Under highly specific internal timing conditions in system configurations that include more than one
processor core, coherency problems may arise between the page tables in memory and the
translations stored in the on-chip TLBs. This can result in the possible use of stale translations even
after software has performed a TLB flush.
Potential Effect on System
Unpredictable system failure. This scenario has only been observed in a highly randomized synthetic
stress test.
Suggested Workaround
In multicore systems, disable the TLB flush filter by setting HWCR.FFDIS (bit 6 of MSR
0xC001_0015).
Fix Planned
No