Specifications

74 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
114 DDR Data Pin Drive Strength Also Affects Command/Address
Pins
Description
Adjusting the drive strength of the DDR data pins by writing to the MemDQDrvStren field in the
DRAM Configuration High register (Dev:2x94[14:13]) also affects the drive strength of the
command/address pins.
Potential Effect on System
Adjusting the drive strength may cause unreliable operation of the DRAM interface.
Suggested Workaround
Do not adjust the DDR data pin drive strength settings in Dev:2x94[14:13]. BIOS should ensure that
these configuration bits remain at the default value of 00b.
Fix Planned
Yes