Specifications

72 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
112 Self-Modifying Code May Execute Stale Instructions
Description
The processor may execute stale instructions in a situation involving a store instruction modifying a
younger instruction within two cache lines of each other and an internal processor trap condition
occurring in a small window:
1. The fetch for the store and the younger instruction must hit in the instruction cache (IC) and are
brought into the processor pipeline.
2. The store speculatively executes, and prior to invalidating the line in the IC, an internal trap event
occurs.
3. This internal trap event must redirect the instruction fetch to a point in the instruction stream just
before the store.
4. The fetch associated with the redirect must hit in the IC before the first execution of the store (in
step 2) has invalidated the line containing the target.
5. During the small window of time between the refetch of the younger instruction and the fetch of
the last instruction in that cache line from the IC, the speculative store from step 2 invalidates the
IC line which contains the younger instruction.
Potential Effect on System
In the unlikely event that the above conditions occur, the processor will execute stale instruction(s).
Just in time (JIT) compilers lack the proximity of the store instruction to the modified code and thus
are not affected.
Suggested Workaround
This scenario was contrived in a highly randomized simulation environment and is not expected to
occur in a real system. In the unlikely event that the erratum is observed, a serializing instruction can
be inserted prior to executing the modified code.
Fix Planned
Yes