Specifications

66 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
106 Potential Deadlock with Tightly Coupled Semaphores in an MP
System
Description
A write location may not become externally visible due to certain internal pipeline conditions
involving tightly coupled semaphores across multiple processors:
1. Processor A does a write to clear processor B's semaphore but that write has not yet become
visible to the system.
2. Processor B is waiting for its semaphore to be released before releasing processor A's semaphore.
3. Processor A immediately enters a spin loop waiting for its semaphore to be cleared by processor
B, and the spin loop must fetch from the instruction cache (IC) on every cycle.
4. Because the IC is busy every cycle combined with other highly specific internal pipeline
conditions, processor A's original write is prevented from being seen by processor B.
Additionally, event 3 (above) must follow event 1 closely in time and interrupts must be disabled.
Potential Effect on System
The system may hang.
Suggested Workaround
In an MP system, BIOS should set LS_CFG.DIS_LS2_SQUISH (Bit 25 of MSR C001_1020h).
Fix Planned
Yes