Specifications

Product Errata 65
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
25759 Rev. 3.79 July 2009
105 Misaligned 128-bit Store May Cause Deadlock
Description
A processor deadlock may occur under the following conditions:
• A 128-bit store operation (MOVUPS, MOVUPD, MOVDQU) occurs to a cacheable memory
type.
• The store is misaligned across two cache lines such that the upper 8 bytes span a cache line
boundary.
• The store has retired but not yet written the data cache.
• The store is followed by two other load or store operations to the same cache index as the second
half of the misaligned store store (i.e., bits 11:6 are the same).
Potential Effect on System
In the unlikely event that the above conditions occur the system may hang.
Suggested Workaround
None.
Fix Planned
Yes