Specifications

48 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
88 SWAPGS May Fail To Read Correct GS Base
Description
The SWAPGS instruction fails to cause an input dependency on the GS segment register. If the GS
segment register has been recently changed via a MOV or POP segment register instruction,
SWAPGS may incorrectly save the old value of GS base into the KernelGSbase MSR.
Potential Effect on System
The KernelGSbase MSR may be corrupted.
Suggested Workaround
Between a MOV/POP into GS and any subsequent SWAPGS there must be a synchronizing
operation. That operation can be one of the following:
• Any of the instructions that are required by the x86 architecture to be serializing
(see AMD64 Architecture Programmer's Manual Volume 2: System Programming, order# 24593).
• A trap, interrupt or exception.
• An SFENCE or MFENCE instruction.
• An instruction that flushes the pipeline:
- CALLF, JMPF, RETF, INTn, IRET, SYSCALL, SYSRET.
The MFENCE alternative is the lowest latency and the recommended alternative. The others are
mentioned in case the code already satisfies them by construction.
Fix Planned
Yes