Specifications

46 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
85 Insufficient Delay Between MEMCLK Startup and CKE Assertion
During Resume From S3
Description
When sequencing the DRAMs out of self refresh during a resume from the S3 (Suspend-to-RAM)
state, the processor fails to insert sufficient delay between MEMCLK startup and CKE assertion.
Potential Effect on System
Memory system failure leading to unpredictable system failure.
Suggested Workaround
Modify the resume from S3 BIOS sequence such that sufficient delay is inserted between the time
MEMCLK is enabled in the DRAM Config High Register (Dev:2x94) and the time the ESR and
SR_S bits are written in the DRAM Config Low Register (Dev:2x90[13:12]) to exit self refresh. For
registered DIMMs, 100 μs of delay is required. For unbuffered DIMMs, 10 μs of delay is required.
Fix Planned
No