Specifications

40 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
78 APIC Interrupt Latency With C2 Enabled
Description
If an APIC interrupt is delivered to the processor at a time when interrupts are masked (i.e.,
EFLAGS.IF=0), and just shortly before entering the C2 power state, then the interrupt may
experience a long latency before being serviced.
The interrupt is not lost, but it is not serviced until some other wakeup event (for example, a timer
tick) occurs to take the processor out of the C2 state.
Potential Effect on System
Excessively long interrupt latencies may occur, resulting in unpredictable system failures.
Suggested Workaround
Do not enable the C2 power state.
Fix Planned
Yes