Specifications

38 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
76 APIC Timer Undercounts In Divide-by-8 Low Power Mode
Description
If S1 or LDTSTOP_L initiated HyperTransport link width/frequency changes are performed with the
Clock Divisor Select (ClkSel) set to divide-by-8, then the APIC timer incorrectly counts at 1/8 its
intended rate. This miscounting remains in effect for as long as the processor remains in the divide-
by-8 mode.
Potential Effect on System
For S1, the divide-by-8 mode is not typically used, so no system implication is expected.
LDTSTOP_L initiated HyperTransport link width/frequency changes do typically use the divide-by-8
ClkSel setting (to minimize latency) and are therefore affected by this erratum. However, for these
operations the time spent in the divide-by-8 mode is limited to approximately 1 μs per use, implying
the APIC timer may lose approximately 0.875 μs each time one of these transitions is performed. This
error would be in addition to any other APIC timer accuracy errors that may exist.
Suggested Workaround
None required. The accuracy loss is small and no observable system impact is expected.
Fix Planned
Yes