Specifications

36 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
74 Registered DIMM Exit-Self-Refresh Requirements Not Met
Description
When sequencing registered DIMMs out of self refresh state at the completion of an S1, S3 or
LDTSTOP_L initiated HyperTransport link width/frequency change, certain sequencing
requirements of the registered DIMMs are not met.
Potential Effect on System
Memory system failure leading to unpredictable system failure.
Suggested Workaround
Do not use S1 S3 on a platform that employs registered DIMMs.
HyperTransport link width/frequency changes must be initiated using warm reset (as opposed to
LDTSTOP_L).
Fix Planned
Yes