Specifications

Product Errata 31
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
25759 Rev. 3.79 July 2009
66 Upstream Read Response Delayed by Downstream Posted
Writes
Description
An upstream read to main memory can be delayed when the following sequence occurs:
1. The processor issues one or more posted writes downstream.
2. The processor evicts a line from its cache.
3. The chipset performs an upstream read to memory with the PassPW bit set in the HyperTransport
packet.
In this case, the read should pass the downstream posted writes but due to a resource conflict in the
internal request queues, the read is delayed until the processor’s cache line is written and all
previously enqueued posted writes have completed.
Potential Effect on System
Unexpectedly large latencies may be experienced during upstream memory reads, potentially
resulting in performance anomalies or functional failures, depending on the buffering capabilities of
external devices.
Suggested Workaround
Limit the number of processor downstream posted requests to one by programming the following
register values:
• Set Dev:3x70[1:0] to 10b (SRI-to-XBAR buffer counts)
• Set Dev:3x7C[5:4] to 00b (Free list buffer counts)
Note that a warm reset is required to allow these new values to take effect.
Fix Planned
Yes