Specifications

Product Errata 21
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
25759 Rev. 3.79 July 2009
51 Arbitrated Interrupt With Illegal Vector Sets APIC Error Bit In All
Processors
Description
If an arbitrated interrupt uses an illegal interrupt vector (0–15), then the corresponding error bit is
erroneously set in the APIC Error Status Register (ESR) of all processors, not just the processor that
accepted the arbitrated interrupt. The accepting processor has its error bit set twice—once during the
arbitration phase (at the same time as all the other processors are erroneously setting their error bits),
and once during the acceptance phase.
Potential Effect on System
If an arbitrated interrupt uses an illegal vector, all processors report that error in their APIC ESR. This
is not expected to impact system operation.
In the case of the accepting processor, the error may appear to be reported twice if software clears the
ESR in the short interval between the arbitration and acceptance phases.
Suggested Workaround
None required.
Fix Planned
Yes