Revision Guide for AMD Athlon 64 and AMD Opteron Processors TM TM Publication # 25759 Issue Date: July 2009 Revision: 3.
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25759 Rev. 3.79 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors July 2009 Revision History Date Revision Description July 2009 3.79 Added errata 147, 352, 353 and 393; Added AMD Athlon™ 64 FX X2 Dual Core Processor (939 package) information; Updated Table 1, Table 3, Table 5, and Table 6. February 2008 3.75 Added erratum #312. October 2007 3.73 Updated Table 5; Updated erratum #122; Updated erratum #169 Suggested Workaround section; Added erratum #181. September 2006 3.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Date 25759 Rev. 3.79 July 2009 Revision Description August 2003 3.07 Added erratum #95, #97, and #98; Modified Description in erratum #94; Added C0 silicon information. June 2003 3.05 Added erratum #94. May 2003 3.03 Added erratum #92. April 2003 3.01 Initial public release.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Revision Guide for AMD Athlon 64 and AMD Opteron Processors TM TM The purpose of the Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors is to communicate updated product information to designers of computer systems and software developers.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 Revision Guide Policy Occasionally, AMD identifies product errata that cause the processor to deviate from published specifications. Descriptions of identified product errata are designed to assist system and software designers in using the processors described in this revision guide. This revision guide may be updated periodically.
25759 Rev. 3.79 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors July 2009 Revision Determination Figure 1 shows the format of the value returned in EAX by CPUID Function 1. Figure 1. Format of CPUID Value Returned by Function 1 Table 1 shows the identification number returned by the CPUID instruction for each revision of the processor. Table 1.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Table 1. 25759 Rev. 3.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Programming and Displaying the Processor Name String This section, intended for BIOS programmers, describes how to program and display the 48-character processor name string that is returned by CPUID Fn8000_000[4:2].
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Processor Name String Table Name String Description 00h AMD Engineering Sample - Reserved 04h AMD Athlon(tm) 64 Processor XX00+ 1 Desktop/DTR Client 05h AMD Athlon(tm) 64 X2 Dual Core Processor XX00+ 1 Dual Core Client 06h AMD Athlon(tm) 64 FX-ZZ Dual Core Processor 3 Desktop/DTR Client 08h Mobile AMD Athlon(tm) 64 Processor XX00+ 1 Mobile Client 09h Mobile AMD Athlon(tm) 64 Processor XX00+ 1 Mobile Client Low Power Mobi
25759 Rev. 3.79 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Processor Name String Table (Continued) Name String Notes Table 3.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Table 4. 25759 Rev. 3.79 July 2009 Model Number Calculation (Continued) # Note 4 TT = 24 + NN. Defined for NN from 000001b to 111111b. For example, 000001b stands for “25” and 111111b stands for “87”. 5 RR = 45 + (5 * NN). Defined for NN from 000001b to 001011b. Reserved for NN from 001100b to 111111b. For example, for NN=000001b RR=“50”, and for NN=001011b RR=”100”. 6 EE = 9 + NN. Defined for NN from 000001b to 011111b.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Product Errata This section documents product errata for the processors. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. Table 5 cross-references the revisions of the part to each erratum. An “X” indicates that the erratum applies to the revision.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Table 5. 25759 Rev. 3.79 July 2009 Cross-Reference of Product Revision to Errata (Continued) X 75 APIC Timer Accuracy Across Power Management Events 76 APIC Timer Undercounts In Divide-by-8 Low Power Mode 77 Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor is Beyond GDT/LDT Limit 78 APIC Interrupt Latency With C2 Enabled X X 79 Power Management Limitations Above 1.
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25759 Rev. 3.79 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors July 2009 Table 6 cross-references the errata to each processor segment. An empty cell signifies that the erratum does not apply to the processor segment. “X” signifies that the erratum applies to the processor segment. “N/A” signifies that the erratum does not apply to the processor segment due to the silicon revision.
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AMD Opteron™ Processor (939 Package) Dual Core AMD Opteron™ Processor (940 Package) Dual Core AMD Opteron™ Processor (939 Package) AMD Athlon™ 64 FX Processor (939 Package) AMD Athlon™ 64 FX X2 Processor (939 Package) AMD Sempron™ Processor (754 and 939 Packages) Mobile AMD Sempron™ Processor Mobile AMD Athlon XP-M Processor AMD Turion™ 64 Mobile Technology 166 X X X X X X X X X X X X X X 169 X X X X X X X X X X X X X X 181 X X X X X X X X X X X X X X 312 X X X X X X X X X X X X X X 352 X X X X X X X
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 1 25759 Rev. 3.79 July 2009 Inconsistent Global Page Mappings Can Lead to Machine Check Error Description If the same linear to physical mapping exists in multiple CR3 contexts, and that mapping is marked global in one context and not global in another context, then a machine check error may be reported by the TLB error detection logic (depending on the specific access pattern and TLB replacements encountered).
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 51 Arbitrated Interrupt With Illegal Vector Sets APIC Error Bit In All Processors Description If an arbitrated interrupt uses an illegal interrupt vector (0–15), then the corresponding error bit is erroneously set in the APIC Error Status Register (ESR) of all processors, not just the processor that accepted the arbitrated interrupt.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 52 Short LDTSTOP_L Deassertion Can Result in Elevated Processor Core Voltage Description While in a low power mode with LDTSTOP_L asserted, if LDTSTOP_L is deasserted and quickly reasserted before the HyperTransport™ links have reinitialized, then an erroneous (elevated) voltage encoding may be driven out on the VID pins.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 57 Some Data Cache Tag Eviction Errors Are Reported As Snoop Errors Description In some cases, the machine check error code on a data cache (DC) tag array parity error erroneously classifies an eviction error as a snoop error. The common cases of cache line replacements and external probes are classified correctly (as eviction and snoop respectively).
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 58 Memory Latency with Processor Power States Description If CPU Low Power mode is enabled in the C1, C2, or throttling processor power states, then externally generated sequences of memory references may experience unexpectedly large latencies through the memory controller.
759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 60 Single Machine Check Error May Report Overflow Description A single parity error encountered in the data cache tag array may incorrectly report the detection of multiple errors, as indicated by the overflow bit of the DC Machine Check Status register (bit 62 of MSR 0x401). Potential Effect on System System software may be informed of a machine check overflow when only a single error was actually encountered.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 61 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation Description Illegal values of ECX (that is, ECX > 3) for the RDPMC (Read Performance Monitor Counter) instruction correctly cause the processor to take a general protection exception.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 62 Task Gates With Breakpoints Enabled May Cause Unexpected Faults Description When a task gate is used by a CALL or JMP instruction and any debug breakpoint is enabled through the DR7.LE or GE bits, the processor may incorrectly use the new TSS base [15:0] contained in the new TSS as a selector. This will most likely lead to a GP fault with an error code of the new TSS base.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 63 TLB Flush Filter Causes Coherency Problem in Multiprocessor Systems Description If the TLB flush filter is enabled in a multiprocessor configuration, coherency problems may arise between the page tables in memory and the translations stored in the on-chip TLBs. This can result in the possible use of stale translations even after software has performed a TLB flush.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 64 Single Step Across I/O SMI Skips One Debug Trap Description When single stepping (with EFLAGS.TF) across an IN or OUT instruction that detects an SMI, the processor correctly defers taking the debug trap and instead enters SMM. Upon RSM (without I/O restart), the processor should immediately enter the debug trap handler.
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25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 66 Upstream Read Response Delayed by Downstream Posted Writes Description An upstream read to main memory can be delayed when the following sequence occurs: 1. The processor issues one or more posted writes downstream. 2. The processor evicts a line from its cache. 3. The chipset performs an upstream read to memory with the PassPW bit set in the HyperTransport packet.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 68 Disable DQS Hysteresis Bit Not Readable Description The DisDqsHys bit of the DRAM Config Low register (Dev:2x90[3]) is writeable and performs its intended function, but it incorrectly always reads as zero to software. Potential Effect on System None expected. This bit is configured by BIOS and readability is not required.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 69 Multiprocessor Coherency Problem with Hardware Prefetch Mechanism Description If the on-chip hardware prefetch mechanism generates a prefetch with write intent for a cache line that is also found to be present in the instruction cache, then the eventual prefetch response from the system is incorrectly discarded by the processor.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 70 Microcode Patch Loading in 64-bit Mode Fails To Use EDX Description When the PATCH_LOADER register (MSR C001_0020h) is written during the installation of a microcode patch in 64-bit mode, the linear address of the patch should be formed by the concatenation of EDX and EAX. The processor incorrectly uses RAX for this operation. Note that patch loading in 32-bit mode is not affected by this erratum.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 71 RSM from SMM with Paging Enabled May Deadlock Description Under a rare set of internal timing circumstances, a speculative TLB reload may incorrectly interact with the RSM instruction such that the processor becomes deadlocked. This can only occur if the SMM handler configures and enables its own paging environment. Potential Effect on System The system hangs and recovers only after a system reset is performed.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 74 Registered DIMM Exit-Self-Refresh Requirements Not Met Description When sequencing registered DIMMs out of self refresh state at the completion of an S1, S3 or LDTSTOP_L initiated HyperTransport link width/frequency change, certain sequencing requirements of the registered DIMMs are not met. Potential Effect on System Memory system failure leading to unpredictable system failure.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 75 APIC Timer Accuracy Across Power Management Events Description The APIC timer may be inaccurate by up to 1 μs across each use of S1or LDTSTOP_L initiated HyperTransport™ link width/frequency changes. Potential Effect on System No observable system impact expected. Suggested Workaround None.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 76 APIC Timer Undercounts In Divide-by-8 Low Power Mode Description If S1 or LDTSTOP_L initiated HyperTransport link width/frequency changes are performed with the Clock Divisor Select (ClkSel) set to divide-by-8, then the APIC timer incorrectly counts at 1/8 its intended rate. This miscounting remains in effect for as long as the processor remains in the divideby-8 mode.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 77 Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor is Beyond GDT/LDT Limit Description If the target selector of a far call or far jump (CALLF or JMPF) instruction references a 16-byte long mode system descriptor where any of the last 8 bytes are beyond the GDT or LDT limit, the processor fails to report a General Protection fault.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 78 APIC Interrupt Latency With C2 Enabled Description If an APIC interrupt is delivered to the processor at a time when interrupts are masked (i.e., EFLAGS.IF=0), and just shortly before entering the C2 power state, then the interrupt may experience a long latency before being serviced.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 79 Power Management Limitations Above 1.50V Description Processor versions with a core voltage greater than 1.50V do not support Northbridge low power mode while in the S1 power state or LDTSTOP_L initiated HyperTransport link width/frequency changes. Potential Effect on System Unpredictable system failures may occur.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 80 Registered DIMM Initialization Requirements Not Met Description When initializing registered DIMMs after a powerup or warm reset assertion, the time interval between the deassertion of MEMRESET_L and the assertion of CKE is not sufficient for some DIMMs. Potential Effect on System The memory system may fail to initialize, leading to boot failure.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 81 Cache Coherency Problem with Hardware Prefetching and Streaming Stores Description If the processor's hardware prefetch mechanism initiates a cache line prefetch at approximately the same time as a streaming store (MOVNT* or MASKMOV*) is performed to that same address, then a stale copy of that line may be loaded into the cache.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 82 Certain Faults On Far Transfer Instructions In 64-Bit Mode Save Incorrect RIP Description This erratum affects the far transfer instructions (CALLF, RETF, IRET, JMPF) in 64-bit mode.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 83 DC Machine Check Extended Error Code Bit Not Writeable Description The extended error code bit in the DC Machine Check Status Register (i.e., bit 16 of MSR 0x0401) cannot be predictably updated by software. When this register is written, bit 16 may be updated to either a zero or a one depending on internal processor conditions.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 85 Insufficient Delay Between MEMCLK Startup and CKE Assertion During Resume From S3 Description When sequencing the DRAMs out of self refresh during a resume from the S3 (Suspend-to-RAM) state, the processor fails to insert sufficient delay between MEMCLK startup and CKE assertion. Potential Effect on System Memory system failure leading to unpredictable system failure.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 86 DRAM Data Masking Feature Can Cause ECC Failures Description Under certain conditions, the memory controller fails to generate a DRAM read request when performing partial writes to an already allocated write combining buffer. Because the DRAM is not read for these subsequent write requests, the generated ECC bits are incorrect. Potential Effect on System Incorrect data can be read back from DRAM.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 88 SWAPGS May Fail To Read Correct GS Base Description The SWAPGS instruction fails to cause an input dependency on the GS segment register. If the GS segment register has been recently changed via a MOV or POP segment register instruction, SWAPGS may incorrectly save the old value of GS base into the KernelGSbase MSR. Potential Effect on System The KernelGSbase MSR may be corrupted.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 89 Potential Deadlock With Locked Transactions Description Downstream non-posted requests to devices that are dependent on the completion of an upstream non-posted request can cause a deadlock in the presence of transactions resulting in bus locks, as shown in the following two scenarios: 1. A downstream non-posted read to the LPC bus occurs while an LPC bus DMA is in progress.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 90 False IC Machine Check Overflow Error Logged On Reset Description If a processor cold or warm reset occurs during a precise window when the instruction cache is being accessed due to a branch re-direct, a false IC Machine Check Overflow error may be logged in the IC Machine Check Status register.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 91 Software Prefetches May Report A Page Fault Description Software prefetch instructions are defined to ignore page faults.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 If the page-fault handler for a kernel can be patched as described in the preceding kernel workaround, no further action by software is required. The following general workarounds should only be considered for kernels where the page-fault handler can not be patched and a prefetch instruction could end up targeting an address in an "inaccessible" page.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 92 Deadlock In Multi-Processor Systems May Occur When Earlier Operations Prevent An Older Store From Writing Data Description A system deadlock may occur in multi-processor systems under the following conditions: 1. Interrupts are disabled. 2. A store operation occurs to a cacheable memory type. 3. The store is retired but not yet written the data cache. 4.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 93 RSM Auto-Halt Restart Returns To Incorrect RIP Description If an SMI occurs on a HALT instruction in 64-bit mode, and the subsequent RSM uses the Auto-Halt Restart feature, the RIP will incorrectly truncate to 32 bits. Potential Effect on System Unpredictable system operation.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 94 Sequential Prefetch Feature May Cause Incorrect Processor Operation Description On an instruction cache miss, the sequential prefetch mechanism may enable the early prefetch of the next sequential cache line. Under a highly specific set of internal pipeline conditions this mechanism may cause the processor to hang or execute incorrect code in 64-bit systems running 32-bit compatibility mode applications.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 95 RET Instruction May Return To Incorrect EIP Description In order to efficiently predict return addresses, the processor implements a 12-deep return address stack to pair RETs with previous CALLs.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 96 Increased Memory Latency During P-State Changes Description The memory controller's idle counters are dynamically managed to help reduce page misses and conflicts. When LDTSTOP is asserted for a P-state (frequency) change, the memory controller incorrectly waits for the idle counters to expire before placing DRAM in self-refresh.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 97 128-Bit Streaming Stores May Cause Coherency Failure Description Under a specific set of internal pipeline conditions, stale data may be left in the L1 cache when a 128bit streaming store (MOVNT*) to a writeback (WB) memory type misses in the L1 data cache and both L1 and L2 TLBs. Potential Effect on System Memory coherence failures leading to unpredictable operation. Suggested Workaround BIOS should set DC_CFG.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 98 LDTSTOP Assertion May Be Missed Description If LDTSTOP width is too short relative to the programmed value of Clock Ramp Hysteresis, the LDTSTOP assertion may be missed. Potential Effect on System FID changes or HyperTransport width/frequency changes may not work correctly. Suggested Workaround Program the Clock Ramp Hysteresis value (Dev:3xD4 [10-8]) to be less than the LDTSTOP pulse width.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 99 Background Scrubbing Must Be Disabled With Non-Contiguous Memory Map Description On some systems, BIOS remaps part of system DRAM above the 4 Gbyte boundary for purposes of reclaiming memory lost to memory-mapped I/O resources. This results in a non-contiguous memory map. The background DRAM scrubber fails when it encounters an area of remapped memory, causing a system deadlock.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 100 Compatibility Mode Branches Transfer to Illegal Address Description An IP-relative branch (call, jump, etc.), while in compatibility mode, may cause the processor to transfer execution to an illegal target address. A specific set of internal pipeline conditions and code alignment must be present.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 101 DRAM Scrubber May Cause Data Corruption When Using NodeInterleaved Memory Description When enabled, DRAM scrubbing cleans ECC errors from memory by performing a read-modifywrite operation of each memory location at a programmable rate. In an MP system, if memory is configured as Node interleaved, the DRAM scrubber may cause data corruption.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 103 AAM or DIV followed by AAM May Produce Incorrect Results Description An AAM (ASCII Adjust after Multiply) or DIV instruction followed closely by an AAM instruction may interfere with each other. This erratum can only occur under a highly specific set of pipeline conditions when AAM is followed by another AAM within 3 instructions, or DIV is followed by AAM within 6 instructions.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 104 DRAM Data Masking Feature Causes ChipKill ECC Failures When Enabled With x8/x16 DRAM Devices Description ChipKill ECC uses 16 ECC bits to correct and detect symbol errors within 128 data bits. If the data masking feature is enabled, the ECC bits are incorrectly calculated for partial writes to memory. This causes incorrect ECC to be written to DRAM.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 105 Misaligned 128-bit Store May Cause Deadlock Description A processor deadlock may occur under the following conditions: • A 128-bit store operation (MOVUPS, MOVUPD, MOVDQU) occurs to a cacheable memory type. • The store is misaligned across two cache lines such that the upper 8 bytes span a cache line boundary. • The store has retired but not yet written the data cache.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 106 Potential Deadlock with Tightly Coupled Semaphores in an MP System Description A write location may not become externally visible due to certain internal pipeline conditions involving tightly coupled semaphores across multiple processors: 1. Processor A does a write to clear processor B's semaphore but that write has not yet become visible to the system. 2.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 107 Possible Multiprocessor Coherency Problem with Setting Page Table A/D Bits Description In a multiprocessor system, a coherency failure may occur in a situation involving a TLB refill, an L1 fill, an L1 victim write, and an external probe, when all four addresses match as described in the following sequence: 1.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 108 CPUID Instruction May Return Incorrect Model Number In Some Processors Description The Model Number field (bits 7-4 of the value returned in EAX by CPUID Function 1) may report an Eh for Revision DH7-CG processors in a 754-pin package. The correct Model Number value for this processor is Ch. The value read from the Model Number field may not be consistent and could report a value of Ch or Eh over time.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 109 Certain Reverse REP MOVS May Produce Unpredictable Behavior Description In certain situations a REP MOVS instruction may lead to incorrect results. An incorrect address size, data size or source operand segment may be used or a succeeding instruction may be skipped. This may occur under the following conditions: • EFLAGS.DF=1 (the string is being moved in the reverse direction).
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.79 July 2009 110 SAHF/LAHF Extended Feature Flag Defaults to Incorrect Value Description The Extended Feature Flag bit defined for SAHF and LAHF instruction support in 64-bit mode is ECX[0]. However some processors that support the feature incorrectly return it as zero. Potential Effect on System The operating system will not see the feature flag and therefore the extended feature will not be used.
25759 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 111 Rtt Specification Violation Description The Rtt specification for the HyperTransport pins may be violated on some processor revisions. TM Potential Effect on System Potential violations of the VID (input differential voltage) and Tr/Tf (slew rate) HyperTransport specifications. There are no known failures related to this problem. Suggested Workaround None required.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 112 25759 Rev. 3.79 July 2009 Self-Modifying Code May Execute Stale Instructions Description The processor may execute stale instructions in a situation involving a store instruction modifying a younger instruction within two cache lines of each other and an internal processor trap condition occurring in a small window: 1.
25759 113 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Enhanced Write-Combining Feature Causes System Hang Description The enhanced write-combining feature provides up to four write-combining buffers, but a potential stall condition can occur when write combining into all four buffers with this feature enabled. Potential Effect on System System hang. Suggested Workaround Disable the enhanced write-combining feature by setting BU_CFG.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 114 25759 Rev. 3.79 July 2009 DDR Data Pin Drive Strength Also Affects Command/Address Pins Description Adjusting the drive strength of the DDR data pins by writing to the MemDQDrvStren field in the DRAM Configuration High register (Dev:2x94[14:13]) also affects the drive strength of the command/address pins. Potential Effect on System Adjusting the drive strength may cause unreliable operation of the DRAM interface.
25759 115 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Data Corruption with Mismatched DIMM Support on 939 Packages Description The mismatched DIMM support feature can cause floating DQS pins on the DDR SDRAM interface. Potential Effect on System Data corruption occurs during DRAM reads when switching from the upper 64-bit memory interface to the lower 64 bits, or vice-versa. The mismatched DIMM feature applies to 939 packages only.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 116 25759 Rev. 3.79 July 2009 DDR Chip Selects Tristated One Clock Early in Power Down Mode Description When entering DDR Power Down mode with the Power Down Tristate feature enabled, the chip selects are tristated coincident with the deassertion of the CKE pins, which is a violation of the DDR specification. Potential Effect on System The DRAM enters an invalid state, resulting in unpredictable system operation.
25759 117 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Incorrect Value May Be Returned When Reading ChipKill ECC Syndrome Description The 16 bits of the ChipKill ECC syndrome are logged in the MC4_STATUS register. During a small window while the processor is updating the syndrome bits for a correctable or uncorrectable error, a read of the MC4_STATUS register may return an incorrect syndrome value.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 118 25759 Rev. 3.79 July 2009 Slew Rate Violation Causes DDR266 RDIMM Failures Description A violation of the Sout specification (DDR slew rate) causes DRAM failures when eight dual-rank registered DIMMs are populated, the memory clock speed is 133 MHz (DDR266), and odd FIDs below 10x are selected. Potential Effect on System Memory corruption resulting in unpredictable system behavior.
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Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 122 25759 Rev. 3.79 July 2009 TLB Flush Filter May Cause Coherency Problem in Multicore Systems Description Under highly specific internal timing conditions in system configurations that include more than one processor core, coherency problems may arise between the page tables in memory and the translations stored in the on-chip TLBs. This can result in the possible use of stale translations even after software has performed a TLB flush.
25759 123 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Bypassed Reads May Cause Data Corruption or System Hang in Dual Core Processors Description An internal data path allows some cache line fill requests to bypass the L2 cache and initiate an early DRAM read before receiving hit/miss status from the cache.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 124 25759 Rev. 3.79 July 2009 STPCLK Throttling Causes Violation of VDD_ac Specification on Some Dual-Core Processors Description STPCLK throttling during maximum power consumption operation generates large load steps and voltage transients that can violate the transient voltage specification (VDD_ac). This problem is exposed on 4-layer motherboards with single power and ground planes when the core frequency is >2000 MHz.
25759 131 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Systems May Deadlock Waiting for a Probe Response Description Under a highly specific and detailed set of internal timing conditions, the Northbridge System Request Queue (SRQ) may stall a probe response leading to a deadlock. Potential Effect on System Deadlock or a machine check error due to a watchdog timer time-out. Suggested Workaround BIOS should set NB_CFG Register[20] (MSR C001_001Fh).
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 135 25759 Rev. 3.79 July 2009 INVLPG Instruction With Address Prefix Does Not Correctly Invalidate the Translation Requested Description When INVLPG is executed with an address size prefix in either 64-bit mode or 32-bit mode, it will not invalidate the requested translation in the TLB. This can result in the possible use of stale translations even after software has performed an INVLPG.
25759 136 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors INVLPG Instruction in 16-bit Mode May Not Invalidate the Translation Requested Description When INVLPG is executed in 16-bit mode without an address size prefix it will not invalidate the requested translation in the TLB. This can result in the possible use of stale translations even after software has performed an INVLPG. Potential Effect on System Unpredictable system behavior.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 147 25759 Rev. 3.
25759 153 Rev. 3.79 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors July 2009 Potential System Hang in Multiprocessor Systems With ≥14 Cores Description Under a highly specific and detailed set of internal timing conditions the crossbar flow control buffer pointer can become corrupted, causing incorrect information to be captured and resulting in a system hang. Potential Effect on System The system hangs.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Dev:0x90h, B0h, D0h LDT Buffer Count Register Settings for Outer Nodes Mnemonic Req PReq Rsp Probe Register Bits [3:0] [7:4] [11:8] [15:12] Coherent Links 1 1 6 4 Non-Coherent Links 5 4 1 0 Dev:3x70h SRI to XBAR Buffer Count Register Settings for Outer Nodes Mnemonic DReq DPReq UReq UPReq URsp Register Bits [29:28] [31:30] [1:0] [5:4] [9:8] 1 1 1 1 1 Value Dev:3x78h MCT to XBAR Buffer Count Register S
25759 Rev. 3.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 154 25759 Rev. 3.79 July 2009 Incorrect Diode Offset Description Some dual-core AMD Opteron™ processors (939-pin package) have an incorrect diode offset (Thermtrip Status Register [DiodeOffset], Dev 3xE4h[13:8]. The affected units can be identified as follows: • CPUID Fn[8000_0001]_EBX(11:0) = 2Ch, and • Thermtrip Status Register [TCaseMax] (Dev 3xE4h[28:25]) <= 2 (53 C).
25759 156 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Read Request Incorrectly Generated for Invalid GART Page Table Entries Description When a read request is made to an invalid address within the GART aperture (i.e., when the valid bit is not set in the GART page table entry), the Northbridge incorrectly generates a read request to the page specified in the GART page table entry (PTE).
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 161 25759 Rev. 3.79 July 2009 Performance-Monitoring Counters Do Not Count Code Address Matches Description The performance-monitoring counters do not count code address matches with DR0-3 unless the corresponding breakpoint is enabled in DR7. Potential Effect on System Performance counters can not be used for instruction address matches when the corresponding breakpoints are not enabled. Suggested Workaround None.
25759 166 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors FXSAVE/FXRSTOR Instructions Use 64-bit Format in Compatibility Mode Description In compatibility mode, FXSAVE/FXRSTOR instructions use the 64-bit memory image format (see figure 11-8 in the AMD64 Architecture Programmer's Manual Volume 2: System Programming, order# 24593) as opposed to the non-64-bit format (figure 11-9).
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 169 25759 Rev. 3.79 July 2009 System May Hang Due to DMA or Stalled Probe Response Description Under a highly specific and detailed set of internal timing conditions, the Northbridge System Request Queue (SRQ) may stall leading to a deadlock. Potential Effect on System Deadlock or machine check exception due to watchdog timer time-out leading to system hang.
25759 181 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Asserting LDTSTOP_L Before DRAM is Initialized May Cause System Hang Description After power up (cold reset), the link frequency is set to 200 MHz, the link width is set to 8, and the processor core frequency may be set below its maximum rated setting. The link frequency and width adjustments can be accomplished using warm resets or LDTSTOP_L.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.
25759 352 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors SYSCALL Instruction May Execute Incorrectly Due to Breakpoint Description A SYSCALL instruction will execute incorrectly and an incorrect debug exception will be taken when all of the following conditions are satisfied: • An enabled instruction breakpoint address matches the RIP of the SYSCALL instruction. • The processor is in 64-bit mode or compatibility mode.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 353 25759 Rev. 3.79 July 2009 SYSRET Instruction May Execute Incorrectly Due to Breakpoint Description A SYSRET instruction will execute incorrectly and an incorrect debug exception will be taken when all of the following conditions are satisfied: • An enabled instruction breakpoint address matches the RIP of the SYSRET instruction. • The processor is in 64-bit mode or compatibility mode.
25759 393 Rev. 3.79 July 2009 Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors Performance Monitor May Count Fastpath Double Operation Instructions Incorrectly Description The processor does not report the correct count for all fastpath double operation instructions when Performance Event Select Register (PERF_CTL[3:0]) MSRC001_000[3:0][EventSelect] is 0CCh. This erratum applies to all unit mask settings for this event.
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors 25759 Rev. 3.
