User Guide

58 General-Purpose Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
The LODSx instructions load a value from the memory location seg:[rSI] to the accumulator register
(AL or rAX). After the load, the rSI register is auto-incremented (if the DF flag is 0) or auto-
decremented (if the DF flag is 1).
Store String
• STOS—Store String
• STOSB—Store String Bytes
• STOSW—Store String Words
• STOSD—Store String Doublewords
• STOSQ—Store String Quadword
The STOSx instructions copy the accumulator register (AL or rAX) to a memory location ES:[rDI].
After the copy, the rDI register is auto-incremented (if the DF flag is 0) or auto-decremented (if the DF
flag is 1).
3.3.11 Control Transfer
Control-transfer instructions, or branches, are used to iterate through loops and move through
conditional program logic.
Jump
• JMP—Jump
JMP performs an unconditional jump to the specified address. There are several ways to specify the
target address.
• Relative Short Jump and Relative Near Jump—The target address is determined by adding an 8-bit
(short jump) or 16-bit or 32-bit (near jump) signed displacement to the rIP of the instruction
following the JMP. The jump is performed within the current code segment (CS).
• Register-Indirect and Memory-Indirect Near Jump—The target rIP value is contained in a register
or in a memory location. The jump is performed within the current CS.
• Direct Far Jump—For all far jumps, the target address is outside the current code segment. Here,
the instruction specifies the 16-bit target-address code segment and the 16-bit or 32-bit offset as an
immediate value. The direct far jump form is invalid in 64-bit mode.
• Memory-Indirect Far Jump—For this form, the target address (CS:rIP) is in a address outside the
current code segment. A 32-bit or 48-bit far pointer in a specified memory location points to the
target address.
The size of the target rIP is determined by the effective operand size for the JMP instruction.
For far jumps, the target selector can specify a code-segment selector, in which case it is loaded into
CS, and a 16-bit or 32-bit target offset is loaded into rIP. The target selector can also be a call-gate
selector or a task-state-segment (TSS) selector, used for performing task switches. In these cases, the