User Guide

40 General-Purpose Programming

AMD64 Technology 24592—Rev. 3.15—November 2009

Immediate Operand Size. In legacy mode and compatibility modes, the size of immediate operands

can be 8, 16, or 32 bits, depending on the instruction. In 64-bit mode, the maximum size of an

immediate operand is also 32 bits, except that 64-bit immediates can be copied into a 64-bit GPR using

the MOV instruction.

When the operand size of a MOV instruction is 64 bits, the processor sign-extends immediates to 64

bits before using them. Support for true 64-bit immediates is accomplished by expanding the

semantics of the

MOV reg, imm16/32 instructions. In legacy and compatibility modes, these

instructions—opcodes B8h through BFh—copy a 16-bit or 32-bit immediate (depending on the

effective operand size) into a GPR. In 64-bit mode, if the operand size is 64 bits (requires a REX

prefix), these instructions can be used to copy a true 64-bit immediate into a GPR.

3.2.3 Operand Addressing

Operands for general-purpose instructions are referenced by the instruction's syntax or they are

incorporated in the instruction as an immediate value. Referenced operands can be in registers,

memory, or I/O ports.

general-purpose registers (GPRs). A few general-purpose instructions reference operands in the

RFLAGS register, XMM registers, or MMX™ registers.

The type of register addressed is specified in the instruction syntax. When addressing GPRs or XMM

registers, the REX instruction prefix can be used to access the extended GPRs or XMM registers, as

described in Section 3.5, “Instruction Prefixes,” on page 71.

Memory Operands. Many general-purpose instructions can access operands in memory. Section 2.2,

“Memory Addressing,” on page 14 describes the g eneral methods and conditions for addressing

memory operands.

I/O Ports. Operands in I/O ports are referenced according to the conventions described in Section 3.8,

“Input/Output,” on page 90.

Immediate Operands. In certain instructions, a source operand—called an immediate operand, or

simply immediate—is included as part of the instruction rather than being accessed from a register or

memory location. For details on the size of immediate operands, see “Immediate Operand Size” on

page 40.

3.2.4 Data Alignment

A data access is aligned if its address is a multiple of its operand size, in bytes. The following examples

illustrate this definition:

• Byte accesses are always aligned. Bytes are the smallest addressable parts of memory.

• Word (two-byte) accesses are aligned if their address is a multiple of 2.

• Doubleword (four-byte) accesses are aligned if their address is a multiple of 4.

• Quadword (eight-byte) accesses are aligned if their address is a multiple of 8.