User Guide

General-Purpose Programming 33

24592—Rev. 3.15—November 2009 AMD64 Technology

Decimal Arithmetic. The decimal arithmetic instructions (AAA, AAD, AAM, AAS, DAA, DAS)

that adjust binary-coded decimal (BCD) operands implicitly use the AL and AH register for their

operations.

Shifts and Rotates. Shift and rotate instructions can use the CL register to specify the number of bits

an operand is to be shifted or rotated.

Conditional Jumps. Special conditional-jump instructions use the rCX register instead of flags. The

JCXZ and JrCXZ instructions check the value of the rCX register and pass control to the target

instruction when the value of rCX register reaches 0.

Repeated String Operations. With the exception of I/O string instructions, all string operations use

rSI as the source-operand pointer and rDI as the destination-operand pointer. I/O string instructions

use rDX to specify the input-port or output-port number. For repeated string operations (those

preceded with a repeat-instruction prefix), the rSI and rDI registers are incremented or decremented as

the string elements a re moved from the source location to the destination. Repeat-string operations

also use rCX to hold the string length, and decrement it as data is moved from one location to the other.

Stack Operations. Stack operations make implicit use of the rSP register, and in some cases, the rBP

decremented when items are pushed onto the stack, and incremented when they are popped off the

stack. The ENTER and LEAVE instructions use rBP as a stack-frame base pointer. Here, rBP points to

the last entry in a data structure that is passed from one block-structured procedure to another.

The use of rSP or rBP as a base register in an address calculation implies the use of SS (stack segment)

as the default segment. Using any other GPR as a base register without a segment-override prefix

implies the use of the DS data segment as the default segment.

The push all and pop all instructions (PUSHA, PUSHAD, POPA, POPAD) implicitly use all of the

GPRs.

CPUID Information. The CPUID instruction makes implicit use of the EAX, EBX, ECX, and EDX

registers. Software loads a function code into EAX, executes the CPUID instruction, and then reads the

associated processor-feature information in EAX, EBX, ECX, and EDX.

3.1.4 Flags Register

Figure 3-5 on page 34 shows the 64-bit RFLAGS register and the flag bits visible to application

software. Bits 15–0 are the FLAGS register (accessed in legacy real and virtual-8086 modes), bits

31–0 are the EFLAGS register (accessed in legacy protected mode and compatibility mode), and bits

63–0 are the RFLAGS register (accessed in 64-bit mode). The name rFLAGS refers to any of the three