User Guide

General-Purpose Programming 31
24592—Rev. 3.15—November 2009 AMD64 Technology
Table 3-1. Implicit Uses of GPRs
Registers
1
Name Implicit Uses
Low 8-Bit 16-Bit 32-Bit 64-Bit
AL AX EAX RAX
2
Accumulator
• Operand for decimal
arithmetic, multiply, divide,
string, compare-and-
exchange, table-translation,
and I/O instructions.
• Special accumulator encoding
for ADD, XOR, and MOV
instructions.
• Used with EDX to hold double-
precision operands.
• CPUID processor-feature
information.
BL BX EBX RBX
2
Base
• Address generation in 16-bit
code.
• Memory address for XLAT
instruction.
• CPUID processor-feature
information.
CL CX ECX RCX
2
Count
• Bit index for shift and rotate
instructions.
• Iteration count for loop and
repeated string instructions.
• Jump conditional if zero.
• CPUID processor-feature
information.
DL DX EDX RDX
2
I/O Address
• Operand for multiply and divide
instructions.
• Port number for I/O
instructions.
• Used with EAX to hold double-
precision operands.
• CPUID processor-feature
information.
SIL
2
SI ESI RSI
2
Source Index
• Memory address of source
operand for string instructions.
• Memory index for 16-bit
addresses.
Note:
1. Gray-shaded registers have no implicit uses.
2. Accessible only in 64-bit mode.