User Guide

General-Purpose Programming 25

24592—Rev. 3.15—November 2009 AMD64 Technology

Figure 3-2. General Registers in Legacy and Compatibility Modes

The legacy GPRs include:

• Eight 8-bit registers (AH, AL, BH, BL, CH, CL, DH, DL).

• Eight 16-bit registers (AX, BX, CX, DX, DI, SI, BP, SP).

• Eight 32-bit registers (EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP).

The size of register used by an instruction depends on the effective operand size or, for certain

instructions, the opcode, address size, or stack size. The 16-bit and 32-bit registers are encoded as 0

through 7 in Figure 3-2. For opcodes that specify a byte operand, registers encoded as 0 through 3 refer

to the low-byte registers (AL, BL, CL, DL) and registers encoded as 4 through 7 refer to the high-byte

registers (AH, BH, CH, DH).

The 16-bit FLAGS register, which is also the low 16 bits of the 32-bit EFLAGS register, shown in

Figure 3-2, contains control and status bits accessible to application software, as described in

Section 3.1.4, “Flags Register,” on page 33. The 16-bit IP or 32-bit EIP instruction-pointer register

contains the address of the next instruction to be executed, as described in Section 2.5, “Instruction

Pointer,” on page 20.

513-311.eps

31 15 016

EAX

EBX

ECX

EDX

ESI

EDI

EBP

ESP

16-bit

low

8-bit

high

8-bit 32-bit

(4)

(7)

(5)

(6)

FLAGS

31 0

FLAGS

EFLAGS

EIP

encoding