User Guide

General-Purpose Programming 23
24592—Rev. 3.15—November 2009 AMD64 Technology
3 General-Purpose Programming
The general-purpose programming model includes the general-purpose registers (GPRs), integer
instructions and operands t hat use the GPRs, program-flow control methods, memory optimization
methods, and I/O. This programming model includes the original x86 integer-programming
architecture, plus 64-bit extensions and a few additional instructions. Only the application-
programming instructions and resources are described in this chapter. Integer instructions typically
used in system programming, including all of the privileged instructions, are described in Volume 2,
along with other system-programming topics.
The general-purpose programming model is used to some extent by almost all programs, including
programs consisting primarily of 128-bit media instructions, 64-bit media instructions, x87 floating-
point instructions, or system instructions. For this reason, an understanding of the general-purpose
programming model is essential for any programming work using the AMD64 instruction set
architecture.
3.1 Registers
Figure 3-1 on page 24 shows an overview of the registers used in general-purpose application
programming. They include the general-purpose registers (GPRs), segment registers, flags register,
and instruction-pointer register. The number and width of available registers depends on the operating
mode.
The registers and register ranges shaded light gray in Figure 3-1 on page 24 are available only in 64-bit
mode. Those shaded dark gray are available only in legacy mode and compatibility mode. Thus, in 64-
bit mode, the 32-bit general-purpose, flags, and instruction-pointer registers available in legacy mode
and compatibility mode are extended to 64-bit widths, eight new GPRs are available, and the DS, ES,
and SS segment registers are ignored.
When naming registers, if reference is made to multiple register widths, a lower-case r notation is
used. For example, the notation rAX refers to the 16-bit AX, 32-bit EAX, or 64-bit RAX register,
depending on an instruction’s effective operand size.