User Guide

14 Memory Model
AMD64 Technology 24592—Rev. 3.15—November 2009
2.2 Memory Addressing
2.2.1 Byte Ordering
Instructions and data are stored in memory in little-endian byte order. Little-endian ordering places the
least-significant byte of the instruction or data item at the lowest memory address and the most-
significant byte at the highest memory address.
Figure 2-5 shows a generalization of little-endian memory and register images of a quadword data
type. The least-significant byte is at the lowest address in memory and at the right-most byte location
of the register image.
Figure 2-5. Byte Ordering
Figure 2-6 on page 15 shows the memory image of a 10-byte instruction. Instructions are byte data
types. They are read from memory one byte at a time, starting with the least-significant byte (lowest
address). For example, the following instruction specifies the 64-bit instruction MOV RAX,
1122334455667788 instruction that consists of the following ten bytes:
48 B8 8877665544332211
48 is a REX instruction prefix that specifies a 64-bit operand size, B8 is the opcode that—together with
the REX prefix—specifies the 64-bit RAX destination register, and 8877665544332211 is the 8-byte
immediate value to be moved, where 88 represents the eighth (least-significant) byte and 11 represents
513-116.eps
Quadword in Memory
Quadword in General-Purpose Register
00h
byte 0
01h
byte 1
02h
byte 2
03h
byte 3
04h
byte 4
05h
byte 5
06h
byte 6
07h
byte 7
063
byte 0byte 1byte 2byte 3byte 4byte 5byte 6byte 7
High (most-significant)
Low (least-significant)
High (most-significant)
Low (least-significant)