User Guide

286 x87 Floating-Point Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
Invalid-operation
exception (IE)
2
FCOS, FPTAN, FSIN,
FSINCOS: Source operand is
∞
or
FPREM, FPREM1: Dividend is
infinity or divisor is 0.
Set IE flag, return the floating-point indefinite value
3
,
and clear condition code C2 to 0.
FCOM, FCOMP, or FCOMPP:
One or both operands is a NaN
or
FUCOM, FUCOMP, or
FUCOMPP: One or both
operands is an SNaN.
Set IE flag, and set C3–C0 condition codes to reflect
the result.
FCOMI or FCOMIP: One or
both operands is a NaN
or
FUCOMI or FUCOMIP: One or
both operands is an SNaN.
Sets IE flag, and sets the result in eflags to
"unordered."
FIST, FISTP, FISTTP: Source
operand overflows the
destination size.
Set IE flag, and return the integer indefinite value
3
.
FXCH: A source register is
specified empty by its tag bits.
Set IE flag, and perform exchange using floating-
point indefinite value
3
as content for empty
register(s).
FBSTP: Source operand
overflows packed BCD data
size.
Set IE flag, and return the packed-decimal indefinite
value
3
.
Denormalized-operand exception (DE)
Set DE flag, and return the result using the denormal
operand(s).
Zero-divide
exception (ZE)
FDIV, FDIVP, FDIVR, FDIVRP,
FIDIV, or FIDIVR: Divisor is 0.
Set ZE flag, and return signed ∞ with sign bit = XOR
of the operand sign bits.
FYL2X: ST(0) is 0 and ST(1) is
a non-zero floating-point value.
Set ZE flag, and return signed ∞ with sign bit =
complement of sign bit for ST(1) operand.
FXTRACT: Source operand is
0.
Set ZE flag, write ST(0) = 0 with sign of operand, and
write ST(1) = –∞.
Table 6-21. Masked Responses to x87 Floating-Point Exceptions (continued)
Exception and
Mnemonic
Type of
Operation
1
Processor Response
Note:
1. See “Instruction Summary” on page 261 for the types of instructions.
2. Includes invalid-operation exception (IE) together with stack fault (SF).
3. See “Indefinite Values” on page 258.