User Guide

284 x87 Floating-Point Programming

AMD64 Technology 24592—Rev. 3.15—November 2009

Each mask bit, when set to 1, inhibits invocation of the #MF exception handler and instead continues

normal execution using the default response for the exception type. During initialization with FINIT or

FNINIT, all exception-mask bits in the x87 control word are set to 1 (masked). At processor reset, all

exception-mask bits are cleared to 0 (unmasked).

Masked Responses. The occurrence of a masked exception does not invoke its exception handler

when the exception condition occurs. Instead, the processor handles masked exceptions in a default

way, as shown in Table 6-21 on page 285.

Table 6-20. x87 Floating-Point (#MF) Exception Masks

Exception Mask

and Mnemonic

x87 Control-Word

Bit

Invalid-operation exception mask (IM) 0

Denormalized-operand exception mask (DM) 1

Zero-divide exception mask (ZM) 2

Overflow exception mask (OM) 3

Underflow exception mask (UM) 4

Precision exception mask (PM) 5

Note:

1. See “x87 Status Word Register (FSW)” on page 241 for a summary of each exception.