User Guide

xxviii Preface

AMD64 Technology 24592—Rev. 3.15—November 2009

RSP

64-bit version of the ESP register.

Stack pointer register.

Stack segment register.

TPR

Task priority register (CR8), a new register introduced in the AMD64 architecture to speed

interrupt management.

Task register.

Endian Order

The x86 and AMD64 architectures address memory using little-endian byte-ordering. Multibyte

values are stored with their least-significant byte at the lowest byte address, and they are illustrated

with their least significant byte at the right side. Strings are illustrated in reverse order, because the

addresses of their bytes increase from right to left.

Related Documents

• Peter Abel, IBM PC Assembly Language and Programming, Prentice-Hall, Englewood Cliffs, NJ,

1995.

• Rakesh Agarwal, 80x86 Architecture & Programming: Volume II, Prentice-Hall, Englewood

Cliffs, NJ, 1991.

• AMD data sheets and application notes for particular hardware implementations of the AMD64

architecture.

• AMD, AMD-K6

MMX™ Enhanced Processor Multimedia Technology, Sunnyvale, CA, 2000.

• AMD, 3DNow!™ Technology Manual, Sunnyvale, CA, 2000.

• AMD, AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets, Sunnyvale, CA, 2000.

• Don Anderson and Tom Shanley, Pentium

Processor System Architecture, Addison-Wesley, New

York, 1995.

• Nabajyoti Barkakati and Randall Hyde, Microsoft Macro Assembler Bible, Sams, Carmel, Indiana,

1992.

• Barry B. Brey, 8086/8088, 80286, 80386, and 80486 Assembly Language Programming,

Macmillan Publishing Co., New York, 1994.

• Barry B. Brey, Programming the 80286, 80386, 80486, and Pentium Based Personal Computer,

Prentice-Hall, Englewood Cliffs, NJ, 1995.