User Guide
244 x87 Floating-Point Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
operand. For details on how each instruction sets the condition codes, see “x87 Floating-Point
Instruction Reference” in Volume 5.
x87 Floating-Point Unit Busy (B). Bit 15. The processor sets the value of this bit equal to the
calculated value of the ES bit, bit 7. This bit can be written, but the written value is ignored. The bit is
included only for backward-compatibility with the 8087 coprocessor, in which it indicates that the
coprocessor is busy.
For further details about the x87 floating-point exceptions, see “x87 Floating-Point Exception Causes”
on page 279.
6.2.3 x87 Control Word Register (FCW)
The 16-bit x87 control word register allows software to manage certain x87 processing options,
including rounding, precision, and masking of the six x87 floating-point exceptions (any of which is
reported as an #MF exception). Figure 6-4 shows the format of the control word. All bits, except
reserved bits, can be read and written.
The FLDCW, FRSTOR, and FXRSTOR instructions load the control word from memory. The
FSTCW, FNSTCW, FSAVE, FNSAVE, and FXSAVE instructions store the control word to memory.
The FINIT and FNINIT instructions initialize the control word with the value 037Fh, which specifies
round-to-nearest, all exceptions masked, and double-extended precision (64-bit).
Figure 6-4. x87 Control Word Register (FCW)
Starting from bit 0, the bits are:
Exception Masks (PM, UM, OM, ZM, DM, IM). Bits 5–0. Software can set these bits to mask, or
clear these bits to unmask, the corresponding six types of x87 floating-point exceptions (PE, UE, OE,
1514131211109876543210
Reserved Y
R
C
P
C
Res
P
M
U
M
O
M
Z
M
D
M
I
M
Bits Mnemonic Description
12 Y Infinity Bit (80287 compatibility)
11–10
RC
Rounding Control
9–8
PC Precision Control
#MF Exception Masks
5
PM Precision Exception Mask
4
UM Underflow Exception Mask
3
OM Overflow Exception Mask
2
ZM Zero-Divide Exception Mask
1
DM Denormalized-Operand Exception Mask
0
IM Invalid-Operation Exception Mask