User Guide

64-Bit Media Programming 205
24592—Rev. 3.15—November 2009 AMD64 Technology
Arithmetic instructions not specifically designated as saturating perform non-saturating, two’s-
complement arithmetic.
Rounding. There is a rounding version of the integer vector-multiply instruction, PMULHRW, that
multiplies pairs of signed-integer word elements and then adds 8000h to the lower word of the
doubleword result, thus rounding the high-order word which is returned as the result.
Other Fixed-Point Operands. The architecture provides specific support only for integer fixed-point
operands—those in which an implied binary point is located to the right of bit 0. Nevertheless,
software may use fixed-point operands in which the implied binary point is located in any position. In
such cases, software is responsible for managing the interpretation of such implied binary points, as
well as any redundant sign bits that may occur during multiplication.
5.5.6 Floating-Point Data Types
All 64-bit media 3DNow! instructions, except PFRCP and PFRSQRT, take 64-bit vector operands.
They operate in parallel on two single-precision (32-bit) floating-point values contained in those
vectors.
Figure 5-9 shows the format of the vector operands. The characteristics of the single-precision
floating-point data types are described below. The 64-bit floating-point media instructions are
summarized in “Instruction Summary—Floating-Point Instructions” on page 223.
Figure 5-9. 64-Bit Floating-Point (3DNow!™) Vector Operand
Table 5-2. Saturation Examples
Operation
Non-Saturated
Infinitely Precise
Result
Saturated
Signed Result
Saturated
Unsigned Result
7000h + 2000h 9000h 7FFFh 9000h
7000h + 7000h E000h 7FFFh E000h
F000h + F000h 1E000h E000h FFFFh
9000h + 9000h 12000h 8000h FFFFh
7FFFh + 0100h 80FFh 7FFFh 80FFh
7FFFh + FF00h 17EFFh 7EFFh FFFFh
63 62
0
3231 30
55 54
23 22
Biased
Exponent
S
Significand
(also Fraction)
S = Sign Bit
Biased
Exponent
S
S = Sign Bit
Significand
(also Fraction)