User Guide

200 64-Bit Media Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
5.4 Registers
5.4.1 MMX™ Registers
Eight 64-bit MMX registers, mmx0–mmx7, support the 64-bit media instructions. Figure 5-7 shows
these registers. They can hold operands for both vector and scalar operations on integer (MMX) and
floating-point (3DNow!) data types.
Figure 5-7. 64-Bit Media Registers
The MMX registers are mapped onto the low 64 bits of the 80-bit x87 floating-point physical data
registers, FPR0–FPR7, described in “Registers” on page 238. However, the x87 stack register
structure, ST(0)–ST(7), is not used by MMX instructions. The x87 tag bits, top-of-stack pointer
(TOP), and high bits of the 80-bit FPR registers are changed when 64-bit media instructions are
executed. For details about the x87-related actions performed by hardware during execution of 64-bit
media instructions, see “Actions Taken on Executing 64-Bit Media Instructions” on page 232.
5.4.2 Other Registers
Some 64-bit media instructions that perform data transfer, data conversion or data reordering
operations (“Data Transfer” on page 209, “Data Conversion” on page 211, and “Data Conversion” on
page 224) can access operands in the general-purpose registers (GPRs) or XMM registers. When
addressing GPRs or XMM registers in 64-bit mode, the REX instruction prefix can be used to access
the extended GPRs or XMM registers, as described in “REX Prefixes” on page 74. For a description of
the GPR registers, see “Registers” on page 23. For a description of the XMM registers, see “XMM
Registers” on page 116.
513-145.eps
MMX
TM
Registers
63 0
mmx0
mmx1
mmx2
mmx3
mmx4
mmx5
mmx6
mmx7