User Guide

186 128-Bit Media and Scientific Programming
AMD64 Technology 24592—Rev. 3.15—November 2009
Invalid-
operation
exception (IE)
Ordered or unordered scalar compare, in which one or both
operands is a NaN (COMISS, COMISD, UCOMISS,
UCOMISD).
Sets the result in rFLAGS to
“unordered.”
Clear the overflow (OF), sign
(SF), and auxiliary carry
(AF) flags in rFLAGS.
Data conversion from floating-point to integer, in which
source operand is a NaN, infinity, or is larger than the
representable value of the destination (CVTPS2PI,
CVTPD2PI, CVTSS2SI, CVTSD2SI, CVTPS2DQ,
CVTPD2DQ, CVTTPS2PI, CVTTPD2PI, CVTTPD2DQ,
CVTTPS2DQ, CVTTSS2SI, CVTTSD2SI).
Return the integer indefinite
value.
Denormalized-
operand
exception (DE)
One or both operands is denormal
Return the result using the
denormal operand(s).
Zero-divide
exception (ZE)
Divide (DIVx) zero with non-zero finite dividend
Return signed infinity, with
sign bit = XOR of the
operand sign bits.
Overflow
exception (OE)
Overflow when rounding
mode = round to nearest
Sign of result is positive
Return +∞.
Sign of result is negative
Return –∞.
Overflow when rounding
mode = round toward +∞
Sign of result is positive
Return +∞.
Sign of result is negative
Return finite negative
number with largest
magnitude.
Overflow when rounding
mode = round toward -∞
Sign of result is positive
Return finite positive
number with largest
magnitude.
Sign of result is negative
Return –∞.
Overflow when rounding
mode = round toward 0
Sign of result is positive
Return finite positive
number with largest
magnitude.
Sign of result is negative
Return finite negative
number with largest
magnitude.
Underflow
exception (UE)
Inexact denormalized result
MXCSR flush-to-zero (FZ)
bit=0
Set PE flag and return
denormalized result.
MXCSR flush-to-zero (FZ)
bit=1
Set PE flag and return zero,
with sign of true result.
3
Table 4-14. Masked Responses to SIMD Floating-Point Exceptions (continued)
Exception
Operation
1
Processor Response
2
Note:
1. For complete details about operations, see “SIMD Floating-Point Exception Causes” on page 178.
2. In all cases, the processor sets the associated exception flag in MXCSR. For details about number representation,
see “Floating-Point Number Representation” on page 127 and “Floating-Point Number Encodings” on page 130.
3. This response does not comply with the IEEE 754 standard, but it offers higher performance.